For the first time, we demonstrate a monolithic three-dimensional (M3D)-integrated 4K electrochemical random-access memory (ECRAM) array with sub-100 nm channels, fabricated atop of the Si-CMOS logic circuits using a back-end-of-line (BEOL)-compatible process (<= 200 degrees C). These devices exhibit significantly low device-to-device variation (sigma/mu similar to 0.026), along with outstanding endurance (5x10(6) pulses). By scaling channel dimensions down to 100 nm through electron-beam lithography, we attain a remarkable 100-fold improvement in programming speed. Full array-level analysis reveals that our proposed M3D-integrated ECRAM-based processing-in-memory (M3D-ECPIM) chip achieves 100% yield and exhibits highly uniform analog switching behavior across the entire 4K array. Additionally, the first chip-level evaluation of symmetry point and half-bias selectivity confirms that both meet the stringent specifications required for neural network training. Finally, the M3D-ECPIM chip demonstrates excellent pattern programming accuracy with only 0.05% error.
Although many pundits have forecasted the growth of edge AI device demand would far surpass the cloud [1] it has not happened yet. AI is widely used in the edge already, but the key killer applications have not evolved. The progress on cloud AI was enabled by AI acceleration with massively parallel compute and high bandwidth access to the memory. On the other hand, the edge device systems are more complex. Four key attributes of the consumer-oriented edge devices are low power consumption, robust connectivity, low cost and large manufacturing scale and these attributes make the edge AI implementations very challenging. Elegant integration and system level optimization of the core compute, AI acceleration, memory access, connectivity, sensing and power delivery blocks are key for edge devices to excel in each of these attributes. This talk will elucidate both the opportunities in front of the community to squeeze more from scaling/power reduction and the need to extend the bandwidth improvements from recent years into the edge devices to achieve the optimal edge system.
We introduce a phase-change memory (PCM) device architecture tailored for analog in-memory computing (AIMC). By confining the active, switchable volume to a compact disc-shaped geometry, this design enables a continuum of non-volatile states programmable at ultra-low currents and power (similar to 40 mu A/mu W), even in standard undoped Ge2Sb2Te5 (GST). Furthermore, the device exhibits a resistance window spanning over three orders of magnitude, while achieving higher overall resistance.
In this work, a DNA synthesis biochip with 256 x 256 resolution fabricated by using indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) technology is presented. A TFT-based gate-on-array (GOA) is also integrated to provide addressing capability for active-matrix driving of 65K pixels. The implemented biochip demonstrated high-throughput synthesis of high- quality oligonucleotides, ranging from 20 to 150 nucleotides in length at femtomole quantities, with optimization of electrode design and driving schemes. The platform maintains compatibility with standard TFT manufacturing processes while eliminating the need for complex photochemical control systems inherent to conventional approaches. This work paves the way for cost-effective, large-scale biochip fabrication, with potential applications in synthetic biology.
Industrial foundry processing of semiconductor spin qubits has revolutionized the scale and yield of quantum processors fabrication, which in turn enables the use of data-driven process optimization and device screening. This requires high-throughput electrical characterization at cryogenic temperatures with complex measurement protocols. Here, we present an investigation of the performance of SiMOS based spin qubit devices made in an optimized 300mm process flow. We showcase how the qubit device uniformity allows efficient characterization using a die-scale cryogenic prober at an effective electron temperature (T-e,T-eff) of 0.8 +/- 0.2 K, which is below the temperature threshold for high-fidelity qubit operation. We leverage machine learning for autotuning the devices and extract key metrics for charge sensor and quantum dot performance for 16 double-dot devices. Our results enable further process optimization as well as variability-aware design of larger SiMOS spin qubit processors.
