Advancements in 2.5D and 3D technology have emerged as breakthroughs within the realm of semiconductor innovation with enhanced performance, efficiency and miniaturization of semiconductor devices. Given the substantial space occupied by SRAM in modern day system-on-chips (SoCs), 3D SRAM promises footprint reduction and enhanced chip performance. Face-to-face (F2F) hybrid bonding is extensively used to bond two or more operational silicon chips to get 3D stacked chips. However, these bond pads have significantly higher pitch when compared with the SRAM bit-cell dimensions and hence the data bandwidth is limited by the bond pitch of the linearly arranged hybrid bond pads. This work demonstrates a staggered pillar configuration to overcome the 3D F2F bond pad pitch limit and hence increasing the bandwidth of the 3D SRAM macro significantly. The 3D SRAM macro with staggered pillar configuration achieves 2x, 4x and 7x improvement in the bandwidth for 400 nm, 700 nm and 1 mu m bond pad pitches, respectively, compared to non-staggered 3D configuration in A14 nanosheet technology.
3D NAND technology is expected to continue advancing toward 1000-layer stacking in pursuit of ever-higher memory density per chip [1]. However, increasing the number of layers presents significant challenges, not only in array stacking but also in the design of the wordline (WL) driver circuits. Each WL requires an independent high-voltage (HV) pass-gate transistor for array operations, and the linear increase in the number of layers directly enlarges the WL driver circuit area, leading to reduced array layout efficiency. In this paper, we propose a novel vertical-channel gate-all-around (GAA) HV transistor. This device leverages the existing 3D NAND Flash manufacturing process, integrated with conventional planar CMOS technology, to enable a new design approach for peripheral circuits in 3D NAND. Based on silicon data from a 3-WL GAA transistor, our TCAD simulations predict that a 24-layer stacked vertical-channel GAA transistor (with an effective channel length of similar to 1.2 mu m in the vertical direction) can achieve a junction breakdown voltage exceeding 20 V, while maintaining sufficient ON-current drivability for WL setup operations. Additionally, incorporating approximately four dummy gates near the drain side as auxiliary gates (AG > 0 V) effectively mitigates GIDL-induced breakdown during the OFF state (Gate = 0 V). This paper outlines the layout design concept and provides device guidelines to enable efficient WL driver designs for the upcoming 1000-layer 3D NAND era.
Hafnium-zirconium oxide (HZO) is a promising ferroelectric (FE) material for non-volatile memories (NVMs) and compute-in-memory (CiM) applications. However, its reliability under bias and temperature stress (BTS) presents a significant challenge, especially for automotive environments. This study presents aluminum-doped HZO (HZAO), which crystallizes within a back-end-of-line (BEoL)-compatible thermal budget while significantly improving BTS stability without compromising key performance parameters. The novel material demonstrates exceptional reliability, operating stably up to 175 degrees C with minimal leakage of 0.02 A/cm(2) during positive-up-negative-down (PUND) testing (+/- 3 MV/cm, 1 kHz). Additionally, HZAO exhibits a recordlow imprint of 0.5V after 12 h of thermal treatment at 200 degrees C, the best performance reported to date for fluorite-structured FE films. These advancements position HZAO as a strong candidate for meeting AEC-Q100 grade 0 requirements in automotive applications.
Bayesian neural network (BayNN) on ReRAM CiM is realized by exploiting the readout variation of ReRAM devices, such as Random Telegraph Noise (RTN), while conventional BayNNs use Gaussian distributions. Multiple samplings in inference are produced by leveraging the change in each readout current due to RTN. By writing LRS to both sides of a differential pair, the mean and standard deviation of the cells can be programmed to fit the weights of the trained BayNN model. Proposed BayNN with CiM noise achieves performance improvements of 9% and 3% compared with conventional NNs for out-of-distribution detection and adversarial attack detection, respectively.
With the rapid growth of data amount in artificial intelligence (AI), near-memory computing (NMC) and in-memory computing (IMC) have emerged as promising solutions to overcome the "memory wall". Traditional storage-centric error-correcting code (ECC) schemes perform error correction on arbitrary bits, introducing significant area and energy overhead. Such bit-level ECC is unnecessary for NMC/IMC architectures, as AI workloads prioritize overall computational accuracy over exact bit correctness. While recent IMC ECC methods focus on computational results rather than bit-level precision, they still lack adaptivity to meet the dynamic precision requirements of AI workloads and the fixed code length results in high area and power overhead.To address these challenges, this paper proposes a precision-adaptive ECC strategy for NMC/IMC for the first time. Our approach dynamically adjusts the encoded data size based on the target workload’s precision requirements and employs an orthogonal compression method to lessen the number of parity bits. By fusing the decoding process into the computational features of NMC/IMC, we reuse existing computational circuits to minimize overhead. Experimental results demonstrate that the proposed method achieves a 45.24% improvement in energy efficiency and a 12.04% reduction in area compared to traditional ECC schemes.
