Advancements in 2.5D and 3D technology have emerged as breakthroughs within the realm of semiconductor innovation with enhanced performance, efficiency and miniaturization of semiconductor devices. Given the substantial space occupied by SRAM in modern day system-on-chips (SoCs), 3D SRAM promises footprint reduction and enhanced chip performance. Face-to-face (F2F) hybrid bonding is extensively used to bond two or more operational silicon chips to get 3D stacked chips. However, these bond pads have significantly higher pitch when compared with the SRAM bit-cell dimensions and hence the data bandwidth is limited by the bond pitch of the linearly arranged hybrid bond pads. This work demonstrates a staggered pillar configuration to overcome the 3D F2F bond pad pitch limit and hence increasing the bandwidth of the 3D SRAM macro significantly. The 3D SRAM macro with staggered pillar configuration achieves 2x, 4x and 7x improvement in the bandwidth for 400 nm, 700 nm and 1 mu m bond pad pitches, respectively, compared to non-staggered 3D configuration in A14 nanosheet technology.
3D NAND technology is expected to continue advancing toward 1000-layer stacking in pursuit of ever-higher memory density per chip [1]. However, increasing the number of layers presents significant challenges, not only in array stacking but also in the design of the wordline (WL) driver circuits. Each WL requires an independent high-voltage (HV) pass-gate transistor for array operations, and the linear increase in the number of layers directly enlarges the WL driver circuit area, leading to reduced array layout efficiency. In this paper, we propose a novel vertical-channel gate-all-around (GAA) HV transistor. This device leverages the existing 3D NAND Flash manufacturing process, integrated with conventional planar CMOS technology, to enable a new design approach for peripheral circuits in 3D NAND. Based on silicon data from a 3-WL GAA transistor, our TCAD simulations predict that a 24-layer stacked vertical-channel GAA transistor (with an effective channel length of similar to 1.2 mu m in the vertical direction) can achieve a junction breakdown voltage exceeding 20 V, while maintaining sufficient ON-current drivability for WL setup operations. Additionally, incorporating approximately four dummy gates near the drain side as auxiliary gates (AG > 0 V) effectively mitigates GIDL-induced breakdown during the OFF state (Gate = 0 V). This paper outlines the layout design concept and provides device guidelines to enable efficient WL driver designs for the upcoming 1000-layer 3D NAND era.
Hafnium-zirconium oxide (HZO) is a promising ferroelectric (FE) material for non-volatile memories (NVMs) and compute-in-memory (CiM) applications. However, its reliability under bias and temperature stress (BTS) presents a significant challenge, especially for automotive environments. This study presents aluminum-doped HZO (HZAO), which crystallizes within a back-end-of-line (BEoL)-compatible thermal budget while significantly improving BTS stability without compromising key performance parameters. The novel material demonstrates exceptional reliability, operating stably up to 175 degrees C with minimal leakage of 0.02 A/cm(2) during positive-up-negative-down (PUND) testing (+/- 3 MV/cm, 1 kHz). Additionally, HZAO exhibits a recordlow imprint of 0.5V after 12 h of thermal treatment at 200 degrees C, the best performance reported to date for fluorite-structured FE films. These advancements position HZAO as a strong candidate for meeting AEC-Q100 grade 0 requirements in automotive applications.
Bayesian neural network (BayNN) on ReRAM CiM is realized by exploiting the readout variation of ReRAM devices, such as Random Telegraph Noise (RTN), while conventional BayNNs use Gaussian distributions. Multiple samplings in inference are produced by leveraging the change in each readout current due to RTN. By writing LRS to both sides of a differential pair, the mean and standard deviation of the cells can be programmed to fit the weights of the trained BayNN model. Proposed BayNN with CiM noise achieves performance improvements of 9% and 3% compared with conventional NNs for out-of-distribution detection and adversarial attack detection, respectively.
With the rapid growth of data amount in artificial intelligence (AI), near-memory computing (NMC) and in-memory computing (IMC) have emerged as promising solutions to overcome the "memory wall". Traditional storage-centric error-correcting code (ECC) schemes perform error correction on arbitrary bits, introducing significant area and energy overhead. Such bit-level ECC is unnecessary for NMC/IMC architectures, as AI workloads prioritize overall computational accuracy over exact bit correctness. While recent IMC ECC methods focus on computational results rather than bit-level precision, they still lack adaptivity to meet the dynamic precision requirements of AI workloads and the fixed code length results in high area and power overhead.To address these challenges, this paper proposes a precision-adaptive ECC strategy for NMC/IMC for the first time. Our approach dynamically adjusts the encoded data size based on the target workload’s precision requirements and employs an orthogonal compression method to lessen the number of parity bits. By fusing the decoding process into the computational features of NMC/IMC, we reuse existing computational circuits to minimize overhead. Experimental results demonstrate that the proposed method achieves a 45.24% improvement in energy efficiency and a 12.04% reduction in area compared to traditional ECC schemes.
This work presents the development of 2D material channels using MoS2 for vertical device architecture and explores their manufacturability in a 300mm fab. We demonstrate conformal ALD MoS2 deposition on structure with high aspect ratio up to 40:1 and develop key downstream unit processes, including atomic-level precision etching, gentle deposition of metal contact, and delamination-free metal CMP on 2D materials. Utilizing an approximate 3D NAND structure with vertical macaroni channels, functional contact formation to the MoS2 channel is demonstrated with electrical data.
An optimized solution for read endurance in OTS-PCM chips is proposed to fulfill the need for the memory hierarchy. A significant increase in error rates was observed after cycling prior to optimization, prompting failure analysis. Selenium migration and GST-OTS intermixing are key failure modes identified by TEM analysis, causing either low-threshold or shorted voltage cells. Simulations showed that BL/WL capacitance reduced OTS spike current during the turn-on process, effectively reducing the primary failure mode found in the failed cells. Optimizing critical dimensions and the total resistance of the devices was proved to improve read endurance by reducing spike current duration, lowering the failure rate from 9% to 0.02%. Furthermore, memory redundancy is incorporated into design to ensure higher failure and error bit tolerance for normal functionality. These solutions are applicable and scalable to SOM and other XPT architecture memory technologies.
Wall type capacitor manufactured by contact/line co-patterning dual damascene (D/D) process was developed to improve capacitance density (CD) for the latest flash memory. In this paper, contact/line co-patterning limitation related with capacitance, and D/D process issues of wall type capacitance were discussed. By employing the wall type capacitor, CD value was increased by 47% with compare to the conventional line trench capacitor, resulting in opportunity of reducing 32% pump capacitor area. In next generation of flash memory including bonding VNAND, further advanced on-chip capacitors having reliable process and high CD have been required. Therefore, ideal scheme for the wall type structure was suggested, and candidates for future capacitor briefly mentioned
Dynamic Flash Memory (DFM) have been fabricated on 300 mm SOI wafers with 65 nm technology, experimentally validating a wide "1" and "0" margin for the first time. The proposed device operates exclusively with positive polarity signals, eliminating the need for negative voltages. Thanks to its unique split-gate structure, a long retention time of over 10 seconds at 85., and a robust Bit Line (BL) disturbance time of 10 ms with the BL stress voltage (VSBL) of 2.5 V are demonstrated.
In this work, we show that in-memory computing using 3D flash memory can be performed at extremely low power consumption. Since the high input voltage of Vpp for the word line (WL) driver circuit is externally supplied, the Vread for the WL voltage of unselected cells and the Vcc for supply voltage to circuits other than the WL driver can be reduced. The power consumption during read operation of single level cell (SLC) is reduced by 56% at Vcc and 98% at Vpp. The significant reduction of memory access energy allows the number of activation blocks and WLs for in-memory computing to be increased. We propose a novel approximate search method that combines the sequential multi-block activation with the current control cell (CC cell). Key vector data is stored in multiple blocks, and query vector data is input as WL voltage, and the on-current of each bit line (BL) is determined by the CC cell. No additional WL control circuit is required, and only one cell is used per data. We demonstrate that the inner product (IP) of the key and the query vector data can be determined with sufficient accuracy for 128-dimensional vectors as well as for 8-dimensional ones. The energy consumption is significantly reduced by 99.4%, and the memory access energy becomes 0.17 pJ/bit. This technology is fully compatible with conventional 3D flash memory and is essential for energy-efficient in-memory computing.
We evaluated and designed the canted angle and magnetic properties of canted spin-orbit torque (SOT) MRAM cells fabricated in a 300mm CMOS fully compatible process. In the results, we demonstrated that 75 degrees-canted SOT devices as SOT-MRAM cell reduced the write power at 0.35 ns field-free writing by 35% and 20% compared to 30 degrees-canted SOT devices [1] and Type Y SOT devices [2], respectively. We also achieved the world's lowest write power of 156 fJ in SOT devices, thanks to the advanced design of both 75 degrees-canted SOT devices and optimized magnetic anisotropy of the MTJ which maintained a large thermal stability factor (Delta) of 70 and a high TMR ratio of 170%. From a viewpoint of stable writing operation at sub-nanosecond, we demonstrated that at a WER of 1E-4 in 0.8 ns writing, the 75 degrees-canted SOT device achieved a lower current density of 20.8 MA/cm(2), which is 43% and 22% lower than the 30 degrees-canted SOT device and the Type Y SOT device, respectively. This study would provide guidelines for the development of canted SOT-MRAM with low power, high speed, and field-free writing.
Transformer-based Large Language Models (LLMs) demand large weight capacity, efficient computing, and high throughput access to large amount of dynamic memory. These challenges present great opportunities for algorithmic and hardware innovations, including Analog AI accelerators. In this paper, we describe recent progress on Phase Change Memory-based hardware and architectural designs to address the challenges for LLM inference.
Zeroth-order fine-tuning eliminates explicit back-propagation and reduces memory overhead for large language models (LLMs), making it a promising approach for on-device fine-tuning tasks. However, existing memory-centric accelerators fail to fully leverage these benefits due to inefficiencies in balancing bit density, compute-in-memory capability, and endurance-retention trade-off. We present a reliability-aware, analog multi-level-cell (MLC) eDRAM-RRAM compute-in-memory (CIM) solution co-designed with zeroth-order optimization for language model fine-tuning. An RRAM-assisted eDRAM MLC programming scheme is developed, along with a process-voltage-temperature (PVT)-robust, large-sensing-window time-to-digital converter (TDC). The MLC-eDRAM integrating two-finger MOM provides 12x improvement in bit density over state-of-the-art MLC design. Another 5x density and 2x retention benefits are gained by adopting BEOL In2O3 FETs.
As NAND flash memory scales and block sizes increase, issues related to reading partially-programmed blocks become more significant. Two concerns of especial significance for such open blocks (OB) are higher ICC during read, and worse reliability degradation due to read disturb (RD). This paper explores these phenomena and presents a novel method to detect and manage them.
A 28 nm split-gate flash in-memory compute technology is evaluated for reliability and accuracy. SST's Embedded SuperFlash((R)), ESF3, memory cell developed for analog compute shows low inference loss and < 2.5% cell distribution widening following 1000 hours high temperature life stresses and endurance cycling. Subthreshold cell current operation of the cell has good immunity to both write and read disturbs.
We developed a Self-Aligned String-Select-Line (SSL) Mold (SASM) scheme where the SSL transistors are independently formed after the main word-line structure, which doesn’t need any dummy hole strings for SSL separation process. The SASM scheme can maximize the gross die by more than 11% by enabling higher density of cell array in the lateral direction. Critical cell characteristics such as erase efficiency, SSL operation window, SSL HCI, cell current, and SSL resistance (SSL RS) are optimized by improving fabrication and operation conditions. The SASM scheme has been successfully integrated in the 9th-generation Vertical NAND (V-NAND) product, suggesting novel memory cell design for next generation V-NAND product with higher bit density and reduced chip size.
Contrary to the general perception of 3D flash memory technology nodes being defined by the vertical stacking of word line layers, we, for the first time, present an unconventional approach employed in the mass production of BiCS FLASHTM generation 8 3D flash technology for achieving similar to 20% increase in bit density primarily with the help of the novel "on pitch select gate" (OPS) technology. This technology relies on cutting several functional select gate drain (SGD) transistors into semi-circular (SC) shapes to achieve lateral scaling. We also discuss some of the major engineering challenges encountered while realizing OPS, and the countermeasures employed to make OPS technology a reality, thereby creating a new path for the future of 3D flash memory industry.
In this work, we compare the memory window (MW) and retention performance of laminated gate stacks for ferroelectric NAND (Fe-NAND) applications, considering both polysilicon and amorphous oxide semiconductor (AOS) channels. The laminated gate stack consists of a 3 nm Al2O3 layer sandwiched between two 8 nm Hafnium Zirconium oxide (HZO) layers. Our results show that AOS channel-based ferroelectric field-effect transistors (Fe-FETs) exhibit a 1.5x larger MW than their polysilicon counterparts at comparable write voltage, primarily due to the absence of a channel interfacial layer (IL) in AOS devices. However, polysilicon Fe-FETs demonstrate significantly better retention, with a retention loss of less than 0.1% at 1000 seconds. In contrast, AOS-based Fe-FETs experience a 37% retention loss at 1000 seconds. We hypothesize that this is due to the presence of oxygen vacancies (Vo(2+)) in the channel, which deplete the electrons over time and increases the depolarization field to cause MW degradation. This study underscores the critical role of channel material selection in optimizing MW and retention performance for Fe-NAND applications.
This paper presents an innovative approach for in-memory Euclidean distance computation with 2T SONOS Flash memory as the computing unit. By utilizing the threshold voltage of Flash cells as stored data, and the input gate voltage as user query, the system can calculate the squared L2/Euclidean distance directly in the array based on the native response of transistor physics, which offers significant advantages in terms of energy efficiency and speed. We introduce an optimized reference current extraction technique, which enhances the accuracy on L2 distance computation despite the non-ideal factors from memory devices. The impacts of Flash device variations and threshold voltage distribution on the recognition accuracy are considered, which further demonstrates the system's robustness against such variations. Simulations showed that the proposed system achieves a recognition accuracy of 94.82% with the Google's FaceNet model and the CelebA dataset, which is comparable to the results with CPU-computed L2 and the cosine-similarity algorithms. The proposed approach highlights the potential of Flash memory-based in-memory computing as an efficient solution for high-accuracy, distance-based applications.
We enable the accurate extraction of the off-current (I-off) values in capacitor-less 2-transistor (2T0C) DRAM cells by developing two experimental methods for assessing the parasitic capacitance (C-para). We thus consider the total storage node capacitance (C-tot = C-oxRtr + C-para) instead of the conventional gate capacitance of the read transistor (C-oxRtr) for the extraction of I-off. The application of these methods to our fabricated IGZO-based 2T0C devices reveals that the correction factor C-tot/C-oxRtr can be more than ten for scaled devices. This is corroborated with simulations for parasitic extraction and subthreshold leakage analysis. Even after applying this correction, our IGZO thin film transistors achieve I-off/W < 5 x 10(-20) A/mu m in 2T0C devices.
