The Y-shaped two-way and four-way Wideband Power Divider (WPD) that can encompass X-band, Ku-band, and ultra-wideband (UWB) is proposed in this letter. Bridging resistors and triangular tapered microstrip line (TTML) are used in the design of the suggested power divider, which is constructed on a low-loss Rogers RT-5880 substrate. Utilizing a corporate feeding network of a 2-way wideband power divider (2WBPD), the Y-shaped 4-way wideband power divider (4WBPD) provides measured insertion loss between -6.16 dB and -14 dB, measured isolation below -16 dB, measured input return loss below -10 dB, and measured output return loss below -10.6 dB in the 2.89 GHz to 18 GHz band. The measured amplitude imbalance is within ±0.13, and the phase difference ranges from 17.2° to -32.03° between output ports. Applications for these wideband power dividers include multistage amplifiers and feeding networks in antenna arrays.
his study expands the understanding of how drain voltage and temperature impact the Negative Bias Temperature Instability (NBTI) effect in Junctionless Nanowire Transistors (JNTs). The electric field within the channel, which is crucial for NBTI, is affected by variations in the voltage between source and drain (VDS), thereby influencing the behavior of space charges. This study demonstrates that the operating regime (induced by the VDS and the temperature) has a significant influence on the variation of the VTH. The results show that the threshold voltage shift (ΔVTH) initially increases with temperature due to its influence on the Fermi potential and flatband voltage. However, beyond 340 K, ΔVTH tends to stabilize or slightly decrease as the device operates closer to the accumulation regime under constant bias conditions. For heavily doped devices, an increase in temperature tends to have little effect on charge mobility, which may ultimately explain the reduced temperature dependence of NBTI observed in JNT devices. This temperature-dependent transition highlights that the NBTI response of JNTs is strongly influenced by the operating regime and bias conditions adopted in this study.
This work examines how device scaling influences the thermal noise performances of InAsxSb1-x n-channel ultra-thin body metal oxide semiconductor (UTB-MOS) for varied lengths of channel, thicknesses of channel, and thicknesses of insulating layer for varying both the gate voltages and the frequencies. To validate the current model, the simulated gate transfer characteristics graph is compared with published experimental results. Based on transconductance (gm) and drain current (ID) simulation results, minimum noise figure (NFmin) , noise resistance (Rn), and the drain current noise spectral density (SID/ID²) were determined. According to our findings, thermal noise in InAsxSb1-x n-channel MOSFETs is dependent on device parameters and can be reduced via suitable device scaling the length of the channel, thickness of channel and thickness of insulator. When the channel length was decremented from 0.1 µm to 0.04 µm at 1V of gate voltage a 0.75 kΩ decrement in noise resistance is achieved . The channel length decrement also yields a power spectral density of roughly 2.2×10⁻²⁴ Hz⁻¹ and a minimum noise figure of roughly 1.3dB .Further improvements were observed with a reduction in channel thickness. Specifically, noise resistance and power spectral density values are significantly lowered when the channel thickness was decreased from 0.1 µm to 0.04 µm at the same gate voltage. A comparative study of the Noise conductance and Input referred noise with respect to frequency for different channel thickness and insulator thickness are calculated and found that the values of Noise conductance and Input referred noise decreases with increment in channel thickness and insulator thickness.
Global arable land shrinks due to rising population pressures, traditional soil-based farming becomes increasingly challenging. To address this, the project aims to design an automatic hydroponic system that operates independently of external climate conditions. This system is capable of growing common crops, indoors for food production. After assessing numerous hydroponic systems for automation compatibility, the ESP 32 microcontroller was selected as the core processing unit, interfacing with many sensors, including as pH, TDS, and DHT11, to enhance system parameters with minimum human oversight. The system utilizes a cloud based IoT platform to monitor, store, and display real-time data for remote access. It ensures optimal plant growth conditions, providing notifications and system status updates. This platform not only supports plant researchers by offering crucial data on system factors affecting plant growth but also aids in enhancing indoor and outdoor farming practices. With automation in place, the system reduces labour-intensive tasks and helps us to make informed decisions by analysing the large amount of data, collected from the different sensors used. Analysis of the results indicates that the automated hydroponic system presents a well-integrated design encompassing both testing and implementation phases. The system demonstrates effective regulation of water and nutrient delivery, while continuously monitoring ambient environmental parameters to support optimal plant growth conditions. Finally, it allows us for growing summer vegetables year-round, regardless of outside weather conditions.
The continuous scaling of CMOS technology has highlighted significant challenges in power consumption and energy efficiency, particularly in arithmetic units of digital systems. This paper presents a novel adiabatic arithmetic unit based on the Junctionless Double-Gate MOSFET (JLDGMOSFET), aiming to minimize power dissipation and enhance energy efficiency. The proposed structure leverages the unique characteristics of the JLDGMOSFET to support adiabatic switching, substantially reducing both leakage power and energy consumption in the subthreshold regime. The proposed adiabatic adder is simulated using SILVACO ATLAS, and its performance is compared against conventional static CMOS adiabatic adders in terms of power dissipation and delay and Power Delay Product (PDP). Simulation results show that the JLDGMOSFET-based arithmetic unit achieves a Power-Delay Product (PDP) reduction of over 85% and a power consumption decrease of up to 90% across a range of supply voltages (0.14 V to 0.30 V), as compared to conventional counterparts. These improvements validate the effectiveness of integrating junctionless device technology with adiabatic logic principles for ultra-low-power arithmetic applications. The proposed approach is particularly suitable for energy-constrained environments such as IoT and biomedical devices, where power efficiency is of paramount importance.
