IEEE Workshop on Microelectronics and Electron Devices : [proceedings]

In this paper, n-MOSFET and p-MOSFET are stressed using Fowler-Nordheim (F-N) tunneling and substrate hot carrier injection (HCI) to induce trapped charges. The inversion mobility is extracted and deconvoluted into surface roughness, phonon, and Coulomb mobilities. Using cryogenic measurement at 4.2K, the effect of phonon scattering is removed, allowing an accurate deconvolution of surface roughness and Coulomb mobilities. It is found that besides the Coulomb mobility being degraded after stress, the effective surface roughness mobility is also degraded.

The increasing adoption of System-in-Package (SiP) devices in critical applications has raised concerns about security vulnerabilities in advanced packaging. The complexity of heterogeneous integration (HI) and 3D architectures exposes critical communication pathways, making them prime targets for adversaries. Traditional inspection methods struggle to identify and expose asset pathways within a package located in deeply embedded structures. In this work, we employ high-resolution X-ray microscopy (XRM) as a non-destructive approach to examine interposer layers, particularly between graphics processing unit (GPU) and high-bandwidth memory (HBM). After identifying regions of interest based on this preliminary scan, we use microwave-induced plasma (MIP) etching to selectively expose interconnects while preserving structural integrity. Focused ion beam (FIB) and scanning electron microscopy (SEM) was used to further enable precise delayering and detailed analysis of interconnect vulnerabilities. This integrated workflow demonstrates how nano-probing attacks in SiP devices can potentially compromise data confidentiality. Our findings highlight the need for robust security measures in advanced packaging architectures.

This study explores the properties of spike timing dependent plasticity (STDP) in spiking neural networks (SNNs) with electrochemical field-effect transistor (ECFET) synaptic devices. STDP is a fundamental unsupervised learning mechanism in neuromorphic computing systems. Electrochemical FETs demonstrate tunable conductance through ionic drift-diffusion processes, offering biologically inspired computation. STDP behavior is demonstrated in ECFETs by analyzing the relationship between input spike timing and frequency, and subsequent modulation of the conductance between ECFET source and drain. Using advanced models that capture the dynamics of real devices, synaptic weight adjustments similar to biological neural plasticity are observed. Impacts of various device parameters on conductance tuning, weight stability are investigated. The findings reveal that ECFETs are an outstanding candidate for synapses in bioloigcally-inspired neuromorphic SNNs.

Constrained Random Verification (CRV) is the de facto standard in ASIC design flow. Parametrized tests are simulated to exercise different execution paths of a Design Under Tests (DUT). These tests are simulated multiple times to generate different test scenarios, by leveraging constrained random stimulus generation. In this work, we propose a methodology utilizing Conditional Tabular Generative Adversarial Network (CTGAN) methodology, conditioned by Upper Confidence Bound (UCB) acquisition function as a reward. The combination of CTGAN and UCB allows the selection of the most relevant test parameters to efficiently navigate the test space and generate new tests. Our methodology, evaluated in live industrial projects, is able to generate new tests, and achieve higher coverage with respect to the baseline generated from the test suite manually created by experienced DV engineers, resulting in an overall coverage improvement of 2.3%.

The increasing reliance on Printed Circuit Boards (PCBs) in critical applications such as defense, aerospace, and secure communications has heightened concerns regarding reverse engineering and counterfeiting threats. Conventional security measures, including cryptographic techniques and physical barriers, face limitations against sophisticated adversarial attacks. This paper explores the potential of integrating reconfigurable Microelectromechanical Systems (MEMS) with PCBs to enhance security. MEMS-based solutions introduce dynamic modifications to PCB characteristics, making reverse engineering more challenging while enabling tamper detection mechanisms. Various adversarial threats to PCB security are examined, alongside the vulnerabilities in the PCB supply chain. This research highlights the urgent need for advanced PCB security mechanisms through case studies of military hardware compromises. This work proposes MEMS-based reconfigurable solutions as a transformative approach to safeguarding PCBs against emerging threats.