Division operation is necessary for many applications, especially optimization algorithms for machine learning. Usually, a certain degree of loss is acceptable in calculating nonsignificant intermediate variables for a considerable speed improvement. This paper proposes a specialized divider to accelerate machine learning optimization algorithm implementation on hardware. Inspired by the fast inverse square root algorithm, we designed a hardware implementation method according to the algorithm, which generates an approximate division result with conversion between floating-point and fixed-point numbers and multiplication. This paper includes three versions of divider: fastDiv accuracy, a conventional design with a 35% less delay and minimal error compared to delay-minimized standard divider from the Synopsys DesignWare library; fastDiv area, an area-oriented design with a 67% less delay and acceptable error compared to the standard divider constrained to the same area size; fastDiv speed, the fastest design with a 54% less delay compared to delay-minimized standard divider. All these three versions can be applied in deploying optimization algorithms in FPGA or ASIC design on demand.
This paper presents a 12/10/8/6-bit successive approximation register (SAR) analog-to-digital converter (ADC) which is compatible with single-ended mode with only one set of SAR logic. Oversampling, dithering and dynamic element matching (DEM) techniques are combined to increase both SNR and linearity to extend accuracy. The proposed ADC is implemented in a 110nm CMOS technology and the total area is 0.194mm 2 • At 1MS/s and VREF=3.3V, ENOB is 11.05b, SFDR is 89.91dB when the input amplitude is 2.97V (-1dBFS) while consuming 742.6uW. The application of DEM helps improve the SFDR by about 4dB. The measured DNL and INL are +/-0.65LSB and +/-1.14LSB respectively. At an oversampling ratio (OSR) of 64, the SAR ADC achieves the ENOB of 13.5b and dither helps improve the absolute accuracy of the DC signal.
This paper presents a V-band low noise amplifier (LNA) implemented in a $\boldsymbol{0.15-\mu} \mathbf{m}$ Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is $\boldsymbol{1.32}\times \boldsymbol{1.5}\mathbf{mm}^{2}$ .
A phase shifter is widely used in the phased array radar system and multi-beam antennas, which enables phased arrays for beam scanning by changing the phase of the corresponding radiating element. Based on GaAs $\boldsymbol{0.15}\mu \mathbf{m}$ process, this work researches and designs a 32-38GHz 6-bit phase shifter, in which the overall size of the chip is 1.87 mm $\times 1.5$ mm. The proposed phase shifter is designed using high and low pass filter types for $\boldsymbol{180}^{\circ}$ and $\boldsymbol{90}^{\circ}$ units. In order to alleviate the problem of too-large inductance and too-small capacitance, this work uses Low-pass and bypass filter types for $\boldsymbol{45}^{\circ}, \boldsymbol{22.5}^{\circ}\boldsymbol{11.25}^{\circ}$ , and $\boldsymbol{5.625}^\circ$ units. The RMS phase shift error of this 6-bit phase shifter is less than $\boldsymbol{4}^{\circ}$ .
Dry electrode interface provides convenient means for continuous biopotential recording, however it requires front-ends with high input impedance to maintain high SNR. This paper proposes a mode change calibration loop (MCCL) for automated input impedance enhancement of capacitively-coupled instrumentation amplifiers (CCIA). To compensate all parasitic capacitors seen at the input nodes which limit the input impedance performance, the MCCL precisely adjusts positive feedback capacitors and automatically converges towards the ideal value. Active shielding is also integrated for cancelling parasitic capacitors outside the chip. Implemented in a typical $\boldsymbol{0.18}-\mu \mathbf{m}$ CMOS process, the post simulation result shows that the front-end consumes $\boldsymbol{4}\ \mu\mathbf{A}$ and achieves $\boldsymbol{1.8}\ \mu\mathbf{V}$ rms input-referred noise over 0.5-100 Hz. After calibration, $\boldsymbol{20}\ \mathbf{G}\Omega$ input impedance at 50 Hz was achieved.
This paper reports a comparative study of wireless power transfer (WPT) circuits implemented using a gallium-nitride (GaN) transistor and its silicon power transistor counterpart. The Colpitts oscillator is adopted for building the WPT circuits and no gate driver circuit is required. The circuit topology allows the simultaneous use of an inductor both as the load at the drain and for inductively coupled WPT. To further minimize power dissipation in the circuit which has a low enough oscillation frequency, a capacitive voltage divider is used to bias the gate of the transistor. Operating at a supply voltage of 15 V and 1.8 MHz, about 70% of wireless transmission efficiency is achieved in both implementations of the WPT circuits. While the GaN implementation is slightly more efficient than the silicon counterpart in the WPT, the performance is not much better, despite the superior GaN transistor properties. Considering the significantly higher cost, GaN transistors have no preferential advantages for WPT circuits over the conventional silicon counterpart, especially when operating at a voltage well below the breakdown voltage. Silicon power transistors are more cost effective in WPT implementations that do not require high power density.
This study proposes a low power circuit design for NAND Flash which is one of the power-hungry devices in datacenters. Power consumption in bit-line (BL) path can be reduced by 60% by utilizing 1.2V I/O power supply instead of 3V power supply, which contributes to reduction in the total power during read operation of 30%. The additional switching circuit only requires silicon area of 0.1mm 2 which is equivalent to 0.1% of a nominal die size of $100\boldsymbol{\text{mm}^{2}}$ . To prevent degradation in sensing margin, the sensing node is pulled up to an internal supply voltage of 2V as used in the conventional design, which is regulated from 3V power supply, before starting sensing operation. This switching operation requires an additional timing of about 100ns which is equivalent to about 2 % of an entire BL delay of $5\boldsymbol{\mu\mathrm{s}}$ . NAND flash interface does not have to be changed because the proposed design can work with the existing interface. BL path and the additional switches were designed in 65nm CMOS. A reduction in power in BL path of 60% was validated with SPICE simulation. As a result, the proposed design can contribute to power reduction in datacenter without any significant overhead on silicon area, BL delay and system design change.
Recent advance in bi-directional neural interface requires miniaturized neural stimulator for implantable applications. Charge balancing circuit is needed to minimize residual electrode voltage after stimulation, hereby avoid tissue damage in long-term usage. This manuscript proposed a dual-mode neural stimulator with charge balancing circuits. With combined continuous current and discrete current pulse compensation techniques, the compensation time is minimized without degradation of accuracy and hardware overhead. The proposed system is implemented in a typical $0.18\upmu \mathrm{m}$ HV process, with integrated high voltage generator. The stimulator was able to deliver 14.4 V pulse and 3 mA current. Compared with conventional charge balancing method, the implemented system achieved 50% compensation time saving with power consumption lower than $18 \upmu \mathrm{W}$ and final residual voltage lower than 7 mV.
Based on 0.18µm SOI process, a fast transient capacitor-less is designed. An LDO with 1.6-2.3 voltage input range, 0-100mA load and 1.5V output voltage is designed. The circuit includes a bandgap reference circuit, a folded structure error amplifier, a super-gm source follower, an active capacitor circuit and an output power stage. Simulation results show that the proposed LDO is stable over the full load range, with a worst-case loop gain of 85dB, PM of 87deg, and GBW>100kHz. This design achieves a load regulation of $\boldsymbol{3\mu}\mathbf{V}/\mathbf{mA}$ , a linear regulation of 9mV/V and a PSR of -33dB. The transient simulation results show that the load jumps from 0 to 100mA in $\boldsymbol{1\mu}\mathbf{s}$ , the overshoot voltage is 57mV, the undershoot voltage is 112mV, and the settling time is $< \boldsymbol{1.5\mu} \mathrm{s}$ . The quiescent current is $\boldsymbol{32\mu}\mathbf{A}$ when the LDO is on, and 630nA when the LDO is off. The temperature characteristic of this circuit is 8ppm/°C, and the circuit layout area is 0.063mm 2 .
Based on the Wiedemann effect, Magnetostrietive Displacement Sensors (MDSs) can measure displacement without contact so that it is free of wear. Therefore, compared with other displacement sensors, the MDSs has a longer service life and is more adaptable to harsh environments. The MDSs are getting more attention and are widely used in industry control system. Precision time interval is the key aspect of the MDSs. In this paper, a pico-second timing system on chip (SoC) is designed in a 180 nm CMOS process for the MDSs applications. SoC is proposed for the MDSs applications. The chip integrates a high speed comparator and a time-to-digital converter (TDC) to build a fine time measurement chain. A 32-MHz microcontroller unit (MCU) realized by RISC-V core with two-stage pipeline is realized for system control. Test results show that the comparator temporal noise is around 1 mV and the TDC achieves a resolution of 156 ps.
This paper presents a GaAs power amplifier (PA). Through the theoretical analysis of the small-signal modeling and large-signal analysis of GaAs transistors, the main influencing factors affecting the saturated output power and gain of a single Gaas transistor are achieved. We develop a low-loss broadband matching by using T-type matching network technology. In addition, the input matching network and the output matching network are used to realize power distribution, which solves the problems of large area and high insertion loss of the traditional power divider in GaasPA. The designed PA is based on a 0.15um GaAs process. The simulation results show that our GaasPA can achieve a saturated output power of 26.7 dBm and a gain of 18 dB in the range of 33-to-37GHz, the DC power consumption is 214 mA at a supply of 5 V, and the chip area is $1.0 \ \mathbf{mm} \ \times \ 1.45 \ \mathbf{mm}$ ,
Keypoint detection is a key procedure for Visual-Inertial Odometry (VIO). In recent years, Convolutional Neural Network (CNN) has been introduced to enhance the robustness of keypoint detection. However, the high computational complexity and memory usage make them difficult to be deployed to edge platforms for high-throughput mobile robot applications such as Unmanned Aerial Vehicles (UAVs) and Autonomous Mobile Robots (AMRs). In this work, we proposed an FPGA-based high-throughput keypoint detection accelerator using CNN with algorithm-hardware co-design, including a lightweight keypoint detection neural network and a dedicated hardware accelerator architecture. Implemented on a Xilinx ZCU104 FPGA board, the proposed accelerator is able to perform keypoint detection at 94 FPS for $640 \times 480$ input image with a low ATE, outperforming the state-of-the-art designs.
This paper proposes a low-power CMOS local-feedback amplifier. The local-feedback amplifier, which has been proposed in [1], has two constant current sources for biasing. They determine the total power dissipation and depend on the maximum amplitude of the input signal voltage. The proposed circuit uses dynamic biasing to reduce the power dissipation when the input signal voltage is small. Results of computer simulations with MOSFET parameters of 0.18 $\mu \mathbf{m}$ standard CMOS technology show similar performance to the conventional one even with reduced power.
This paper presents several innovative low power techniques to design an ultra-low power SAR ADC for ECG application. Body driven (BD) or biasing (BB) techniques are used in bootstrapped switches and SAR logic to minimize leakage power consumption. In addition, we propose a dynamic comparator with a floating inverter amplifier (FIA) architecture with a modified strong-arm latch and a BD input stage to reduce the noise and offset by reducing the noise current and eliminating the influence of common-mode input voltage. Lastly, the VCM based switching scheme allows a fixed common-mode input voltage swing, relaxing the offset requirement of dynamic comparator. The proposed SAR ADC is implemented in a 180nm CMOS process. The whole ADC consumes 41nW at a sampling rate of 10kS/s under a supply of 0.6V, obtaining the ENOB of about 10bit and resolution of 10bit.
Sensors for industrial generally monitor slowly changing variables and output data in relatively lower throughput. Therefore low speed and low-cost data converters have their advantages. Pulse-width Modulation on Digital-to-Analog Converter (PWM DAC) meets the requirements of industrial applications. It has the advantages of ease to access and low cost and is not sensitive to semiconductor processes. This paper presents the design of a 14-bit PWM DAC, where a delay line with 625ps resolution is integrated to allow higher DAC resolution without raising the clock frequency.
This paper proposes an improved grid-connected system with PhotoVoltaic (PV) and battery storage under non-uniform irradiance conditions. We first develop an implementation of the system while considering non-uniform Partial Shading (PS) conditions which several literatures do not consider. Next, we propose an improved PV Maximum Power Point Tracking (MPPT) algorithm, which have shown its superiority for non-uniform irradiance conditions compared to another MPPT algorithm specifically in terms of power convergence efficiency. Finally, we validate the performance of the grid-connected architecture by showing battery charging and discharging in situations of excess and deficient PV supply and also the grid supplying to the load in case of deficiency in both battery State of Charge (SoC) and PV supply.
Semi-global matching (SGM) is a canonical depth estimation algorithm widely used in the fields of autonomous driving, 3D reconstruction, and SLAM. However, high complexity withholds its application in high-speed and low-power depth extraction scenarios, notably in IoT and edge devices. To tackle these problems, we propose a region-optimized SGM algorithm, which can alleviate memory consumption bottleneck and strike a balance among power dissipation, processing speed, and resource consumption. First, we design a fully parallel initial matching costs calculation architecture, which ensures synchronization of the left and right pixel stream. Then, a two-layer parallel two-stage pipeline structure (TPTP) calculates the cost aggregation in two directions (0° and 135°) to mitigate the high computational complexity. Finally, we adopt a LUT-based cosine sub-pixel interpolation architecture and a multi-directional parallel hole filling architecture (MPHF) to improve accuracy further in the disparity refinement process. The experimental results show that the proposed pixel-level pipeline architecture achieves a processing speed of 320 frames per second (fps) at 98MHz on the Stratix-IV FPGA device.
In recent years, there has been a strong interest in low-power low complexity localization systems based on the electromagnetic properties of the interacting signals. Reducing power and complexity are key requirements especially for the fast-growing number of applications based on the Internet of Things (IoT) paradigm. In this paper we propose a novel technique for the Angle of Arrival estimation based on phase interferometry. The technique is fully digital and synchronous and its major advantage relies on the simple hardware implementation and modularity. The approach was validated on a Cyclone IV E EP4CE115F29C7 FPGA and showed very promising preliminary results.
As semiconductor devices become smaller and smaller, device aging simulation plays an increasingly important role in the overall circuit design. In recent years, the research of device aging modeling has gradually become the focus of researchers. Most of the current aging modeling methods only consider the degradation of one parameter, resulting in inaccurate simulation of the model in actual testing. In response to this problem, this paper establishes an HCI(Hot Carrier Injection) aging model on NMOS devices, focusing on the simultaneous degradation of multiple parameters (drain current in saturation region (I-dsat) and threshold voltage (v(th)) in the process of extracting model parameters. Simulation results show that this method can improve the fitting accuracy of aging model.
A heat energy source with automatic control of supply can make it safer and reliable for users. In this study, networks of sensors are proposed that can be utilized for detecting drastic temperature change to design a controlled and safe heat source. As a feasibility study, experiments are performed to explore the effectivity of proposed network with circuit parameters. An array of sensors-for the detection of irregular or accidental temperature deviation-is proposed for ensuring a safe heat source through real time monitoring. The results indicate the potential of using the network with given constraints for use in the control circuitry design.
