Due to the desire to further improve the energy efficiency and performance of ultra-low power (ULP) radio frequency (RF) circuits. In recent years, the growing demand for Internet of Things (IoT) devices has required efficient design methodologies. However, confronting the trade-off becomes difficult. Therefore, this paper proposes a systematic sizing methodology for low-noise transconductance amplifiers (LNTAs) based on normalized biasing metrics and pre-calculated lookup tables. This approach aims to optimize the inherent tradeoffs between gain, noise, linearity, and power consumption. The methodology was applied to design and compare six variations of a 5.8 GHz LNTA implemented in 65 nm CMOS technology. The comparative analysis demonstrates that the normalized biasing metric offers the best compromise, achieving a Figure of Merit (FoM) of 180.8 GHz with a power consumption of only 147.5 µW. This approach provides a structured design flow that allows designers to quickly identify an optimal operating point and thus accelerate the development of efficient RF front-ends for power-constrained IoT applications.
The continuous scaling of semiconductor technology drives the demand for integrated circuits with higher performance and smaller area. In this context, standard cell libraries play a key role in optimizing digital designs. This paper presents the ASIC implementation of the PicoRV32 RISC-V CPU using a 4.5-Tracks multi-height standard cell library tailored for 7nm FinFET technology. While multi-height libraries are established, the novelty of this work lies in the practical demonstration of a complete back-end implementation, including logic synthesis, placement, routing, and area optimization. The utilization of the proposed 4.5-Tracks library achieves a 29% reduction in overall core area compared to a conventional 6-Tracks library, with DFFR and XNOR2 cells contributing most to this reduction. These results highlight the effectiveness of multi-height cells in real-world designs and provide practical guidance for future area optimized RISC-V ASIC developments.
The symmetrically built MOS transistors of integrated circuits exhibit symmetric electrical behavior if the source and drain terminals are interchanged. Additionally, a series association of transistors is electrically “equivalent” to a single transistor. However, some of the compact MOSFET models do not comply with the requirements of symmetry and transistor equivalence. This paper reports tests of symmetry and of series association of transistors of some compact models available in circuit simulators. We show that the ACM2, a chargebased model in which the terminal voltages are referred to the substrate, is fully compliant with the transistor symmetry, but that some popular models are not. To test the symmetry property, we show examples of transistor current-voltage characteristics and derivatives up to the fifth order, and capacitance-voltage characteristics, all tests around $V_{D S}=0$. A MOSFET binary current divider is employed to test the consistency of the model applied to a series association of transistors.
This paper presents the design of an open-source wireless power and data transfer (WPDT) unit for implantable and wearable medical devices (IWMD) using a parameterized-cells (P-Cells) library of commonly used building blocks. The P-Cells are designed with open-source design tools Ngspice and Xschem, and use Python as modeling and scripting language. Based on input specifications, four blocks including a capacitor bank, load-shift keying modulator, full-wave rectifier, and low-dropout regulator have been automatically designed using the P-Cells. To highlight the versatility of our approach, two units with different load specifications have been implemented in the open-source IHP SG13G2 130 nm process. Simulation results demonstrate agreement with the specifications and the viability of our approach.
This paper presents an ultra-low-power hardware architecture for muscle fatigue detection based on the discrete Haar Wavelet transform (DHWT). Surface electromyography (sEMG) signals are processed using a 4-level (D4) discrete Wavelet transform (DWT) to extract mean (MNF) and median (MDF) frequency features, key indicators of muscle fatigue. Our DHWT explores the techniques of pruning and approximation. The pruning eliminates redundant arithmetic modules that are unimportant for muscle fatigue detection. The approximation DHWT (ADHWT) replaces conventional adders with approximate adders (AxAs), such as COPY, ETA-I, LOA, Truncation (TRUNC), and AxPPA. The ADHWT maintains the effectiveness of the muscle fatigue detection, while significantly saving 96.01% energy and 94.16% area. The ADHWT with the AxPPA represents the best trade-off between the energy- and area-savings versus maintaining the ability to detect muscle fatigue.
