Wideband noise degradation from 10 MHz to 26.5 GHz—covering the flicker and thermal regimes— is characterized in commercial 5-nm n-channel FinFETs under non-conducting RF hot-carrier stress, motivated by the off-state portion of the LC voltage-controlled oscillator (VCO) cycle. A single-instrument, single-probing methodology based on a PNA-X with noise option is used to apply RF stress and measure both scattering (S-) parameters and 50 Ω noise figure over the full bandwidth, eliminating instrument switching and probe-handling errors and reaching well above the GHz-range flicker-noise corner. Stress-induced changes in Id, the RF transconductance G21, the drain-current noise power spectral density (PSD) SId, and the gate-referred voltage-noise PSD SVg are analyzed across gate bias, peak drain stress voltage Vd,max, and stress frequency. The drain-current degradation reflects competing oxide hole trapping and interface-trap charging, while ΔSVg is positive in the lifetime window and follows a power law, making it the robust noise-reliability monitor. Comparison of 2 GHz and 5 GHz stress shows a measurable stress-frequency dependence in ΔSVg , motivating lifetime extraction directly from RF stress data rather than from DC-based quasi-static projections. Using a 100% increase of SVg as the lifetime criterion—doubling the transistor flicker-noise contribution to oscillator phase noise—a Takeda-form 1/Vd,max model fitted to the RF data projects a maximum Vd,max of ≈2 V for a 10-year noise lifetime, comfortably above the 2Vdd = 1.5 V condition typical of LC-VCO operation at the nominal Vdd = 0.75 V supply, confirming the suitability of 5-nm FinFETs for RF circuits with stringent phase-noise targets.
In this paper, we propose a domain-specific unsupervised comparison-based anomaly detection (AD) framework for semiconductor inspection. Due to the rarity of defects in semi-conductor devices, it is impractical to collect sufficient labeled defective data for supervised learning. Therefore, unsupervised AD methods are promising alternatives that learn representations of normal data and identify anomalies as deviations from the learned representations. However, most existing unsupervised AD methods struggle to identify abnormal regions in complex and intricate normal patterns that are frequently observed in semiconductor products. To address this challenge, leveraging the unique repetitive structure of semiconductor devices, we propose a comparison-based AD system that compares a test device with its corresponding reference device. Specifically, our method utilizes a weight-shared twin encoder to compare test and reference images in a shared feature space. We then refine each feature map through a projection-based co-attention (PCA) module which estimates channel correlations and registration errors using horizontally and vertically projected feature maps to effectively suppress false positives arising from pseudo changes (e.g., misalignment or illumination variation). Based on these refined maps, we compute difference features that tend to concentrate near zero in normal regions while producing larger deviations in defective regions. Finally, these features are fed into a pixel-wise decoder for defect localization and into a normalizing flow (NF) network for density estimation of normal data.
This paper presents the implementation of a robust fault detection and classification (FDC) framework for automated photolithography process monitoring in high-mix, high-volume compound semiconductor manufacturing. A proprietary data extraction and processing solution was developed to integrate wafer-level and intra-exposure-field stepper data into a scalable production FDC system. The framework enables inline detection of focus, tilt, alignment, and exposure dose anomalies during the stepper exposure process. Several case studies are discussed to demonstrate its effectiveness in identifying and preventing process and tool excursions that affect device performance. By enabling immediate tool and lot disposition, the system reduces excursion propagation, wafer scrap, and yield loss while accelerating troubleshooting through centralized process visibility. Deployment of the framework into production improved critical dimension (CD) and overlay control, reduced unscheduled equipment downtime, boosted fab productivity, and resulted in significant yield improvement.
We introduce a novel deep learning framework for etch proximity correction (EPC), termed differentiable EPC (DEPC), which enables end-to-end optimization of after-etch patterning prediction and subsequent semiconductor layout correction. Unlike conventional EPC methods that rely on local corrections, this approach enables collective pattern optimization. The framework utilizes a transformer architecture incorporating relative coordinate encoding and masked attention to process layout data represented as polygons, thereby eliminating the prediction model’s patch dependency to scales well below the database-unit level. Additionally, we propose an inverse differentiable correction algorithm that enables convergence of targeting-off values within a database-unit level threshold across the entire chip layout. Using synthetic data generated to represent real-world semiconductor fabrication scenarios, we evaluated the performance of our proposed method and found that it reduces prediction error by 6.6% compared to hybrid ML model-based EPC and lowers revision verification scenario error by 6.5%, while maintaining accuracy close to the stochastic noise limit. The embedded‑space inclusion analysis indicates the usefulness of perturbative training samples within design‑rule bounds, enabling coverage of the corrected‑layout embedded space. By reducing variability in critical dimensions and improving targeting accuracy, this approach contributes to improved process margins and manufacturability in semiconductor fabrication.
With the continuous reduction of feature sizes in integrated circuits, the optical proximity effect has become a critical factor limiting the yield of chip manufacturing. As a vital resolution enhancement technique, inverse lithography technology enables pixel-level optimization of masks. However, traditional methods typically exhibit weak generalization and robustness when encountering new layouts with variations in shape, density, or position; moreover, the iterative refinement processes significantly degrade mask optimization efficiency. In this paper, we develop a Flow Matching-based Inverse Lithography Technique (FM-ILT) framework. A lithography simulation model is embedded into the training framework to constrain the fidelity and complexity of mask optimization via lithography regularization loss terms. The proposed FM-ILT learns probabilistic paths from the data to characterize mask optimization rules, enabling adaptive optimization for unseen layout patterns. The deterministic optimal transport path accelerates model convergence and stabilizes the training process. Experimental results on the LithoBench benchmark demonstrate that the proposed framework generates masks with excellent imaging fidelity, exhibiting strong generalization to unseen patterns and robustness to process variations. Furthermore, the end-to-end architecture significantly enhances mask optimization efficiency.
In this work, a novel blanket germanium (Ge) ion implantation process is demonstrated to be able to suppress the drain-induced barrier lowering (DIBL) for PMOSFETs with the embedded SiGe source/drain (S/D). To suppress the DIBL, a higher doping level is usually applied in the halo region, which will unavoidably result in the unexpected increase of the absolute value of threshold voltage (|Vt|). It is revealed that the proposed additional blanket Ge ion implantation process can effectively enhance the hole current in the channel during on-state, i.e., lowering the |Vt|, and suppress the out-diffusion of B into the channel region from the lightly doped drain (LDD) region at the same time. Hence, compared to PMOSFETs without the blanket Ge ion implantation, the DIBL can be significantly reduced for more than 15% without the negative impact on device performance. The proposed process does not require additional masks, thereby not significantly increasing the complexity or cost of the overall process, providing the great application potential for PMOSFETs with the embedded SiGe S/D.
Lithographic hotspot detection is essential for improving the yield of integrated circuit manufacturing. Although convolutional neural networks have achieved promising performance in this task, their reliance on high-resolution layout images often leads to substantial computational and storage overhead as feature sizes continue to shrink. This paper proposes a compact graph-based hotspot detection method, named Distance-Enhanced Attentional Graph Isomorphism Network (DEA-GIN). In the proposed framework, layout clips are first converted into graph-structured representations, where geometric primitives are modeled as nodes and their spatial relationships are encoded through graph edges. This representation preserves key layout information while significantly reducing the input data volume compared with pixel-based images. To further capture spatial proximity among layout components, an edge distance attention mechanism is designed to modulate message passing according to the Euclidean distances between connected nodes, enabling the model to focus on critical local interactions that are more likely to induce lithographic hotspots. The proposed attention mechanism is integrated into a lightweight Graph Isomorphism Network to improve hotspot classification with limited model complexity. Experimental results on benchmark datasets show that DEA-GIN achieves detection accuracy comparable to representative CNN-based methods, while reducing the model size by one to two orders of magnitude and improving model-inference speed by more than tenfold. Compared with previous GNN-based methods, DEA-GIN provides a more compact model and approximately half the inference time, while maintaining a favorable recall – false-alarm trade-off. These results demonstrate the potential of DEA-GIN for scalable and efficient hotspot detection in advanced VLSI design flows.
Classical run-to-run (R2R) controllers for chemical mechanical planarization (CMP)—the double exponentially weighted moving average (D-EWMA) and the Kalman filter—share a reactive structure: they observe removal-rate (RR) error after each wafer lot and issue a corrective recipe for the next. As wear shifts the process gain between lots, each correction is mismatched to the current state and recipe oscillation grows as consumables age. This paper reformulates CMP R2R control as an offline reinforcement learning problem and proposes SARC (State-Adaptive R2R Controller), an offline RL framework that avoids online exploration by replacing reactive error correction with proactive wear adaptation. A Drift Encoder, pre-trained via an auxiliary RR-prediction task, distills wear telemetry into a 2-D context vector; a conservative Q-learning (CQL) policy regularized toward the behavioral distribution then maps the state–context pair to zone-pressure recipes. We evaluate SARC on a CMP drift simulator (mild and medium drift), the public Prognostics and Health Management (PHM) 2016 benchmark, and a 23,802-wafer industrial fab dataset. On both fab datasets, in model-based evaluation, SARC attains the lowest RR tracking error among the controllers compared without inflating control effort, improving the accuracy–stability trade-off of reactive R2R control. Ablation studies identify the Drift Encoder as the source of the recipe-stability gains.
AI-based semiconductor defect inspection is often limited by the scarcity of real defect samples, particularly for slender crack-like defects that occupy only a small number of pixels and exhibit subtle contrast against complex backgrounds. To address this limitation, we propose Latent Anomaly Blending Network (LABNet), a lightweight two-stage framework for one-shot synthesis of slender industrial defects from a single defect image and its binary mask. In the first stage, LABNet learns normal and defective image-domain representations using adversarially regularized autoencoders. In the second stage, it performs mask-guided high-resolution latent blending and decodes the blended representation with a locality-aware discriminator, preserving the normal background while generating realistic defect textures. The latent-mask formulation further enables controllable manipulation of defect position, count, and morphology without iterative diffusion sampling or per-image optimization. Experiments on industrial optical-inspection data show that LABNet achieves competitive synthetic image quality, efficient inference, and improved downstream defect detection and localization performance compared with representative blending-, GAN-, and diffusion-based baselines. Additional ablation and robustness analyses further support the effectiveness of high-resolution latent blending and local adversarial supervision for one-shot slender-defect synthesis.
MiniLED technology has emerged as a critical solution in the high-end display industry. However, its manufacturing process is susceptible to various defects. In MiniLED defect detection, the available defect data are typically limited, while defect categories exhibit substantial variations in spatial scale. This combination severely hinders effective multi-scale representation learning, causing existing methods to struggle with accurate defect recognition. To address these challenges, this paper proposes an efficient scale-aware learning framework, termed SAL-Net, for high-precision MiniLED defect detection. In SAL-Net, a progressive unfreezing transfer learning strategy is designed for the encoder to alleviate insufficient feature learning caused by limited training data. By gradually releasing pretrained parameters from high-level semantic stages to low-level fine-grained stages, this strategy enables more effective adaptation of pretrained knowledge to the pronounced scale diversity of MiniLED defects. Its effectiveness is systematically validated through comparison with three representative transfer strategies. Furthermore, an efficient multi-scale interaction (EMI) attention module is proposed to enhance feature discriminability, thereby strengthening the perception capability for defect regions. Subsequently, the decoder leverages progressive upsampling and top-down cross-scale feature compensation (TCFC) operations to facilitate multi-level feature aggregation. Extensive experiments on a MiniLED dataset demonstrate that SAL-Net achieves 93.47% mF1, 87.91% mIoU, and 75.89% IoUF , outperforming 13 state-of-the-art methods. Meanwhile, SAL-Net contains 15.90M parameters with an inference speed of 77.25 FPS, providing a favorable balance between detection accuracy and computational efficiency.
With the continued scaling of integrated circuits, maintaining high manufacturing yield has become increasingly difficult, which places greater demands on effective defect root cause analysis (RCA). Most existing image-based RCA methods rely on single-modality defect images, which limits their ability to fully characterize defects that exhibit complex structures across different observation levels. In this work, we propose a lightweight deep learning framework, referred to as DRCNet, for retrieval-based defect RCA in semiconductor manufacturing. Given a query defect, DRCNet retrieves similar historical cases at the root-cause level. The framework jointly leverages optical inspection images and scanning electron microscope (SEM) images to capture complementary macroscopic and microscopic defect information. To effectively integrate features from different modalities, a cross-attention-based fusion strategy is adopted. In addition, a lightweight multi-scale feature fusion module is introduced, together with a joint loss function that combines triplet loss and weighted cross-entropy loss, to improve feature discriminability for retrieval. Experiments conducted on real semiconductor manufacturing defect datasets show that the proposed method significantly outperforms representative state-of-the-art defect recognition and image retrieval approaches. In particular, DRCNet achieves a substantial improvement in mean average precision (mAP), reaching 75.76% on the evaluated dataset. Despite its improved performance, the framework remains computationally efficient, making it suitable for practical deployment in manufacturing environments.
To address the challenges of high missed detection rates and low localization accuracy in existing wafer surface scratch detection algorithms, this paper proposes WSD-YOLO, a lightweight scratch detection method for backend packaging AOI inspection. First, the method introduces a strip convolution block to effectively suppress interference from background texture noise. Second, it integrates the content-aware attentional multi-scale aggregation module to recover high-resolution spatial details and reinforce feature semantic consistency and spatial localization capabilities. Moreover, the detection head is optimized by replacing the low-resolution P5 layer with a high-resolution P2 layer, which significantly enhances detection precision for extremely tiny targets. Finally, a task-oriented hybrid loss, termed Dynamic Angle-Inner IoU (DAI-IoU), is employed by combining SIoU, Inner-IoU, and Wise-IoU to improve bounding-box regression for slender micro-scratches. Experiments on the self-constructed dataset show that WSD-YOLO achieves 79.5% precision, 84.3% recall, 84.8% mAP50, and 46.3% mAP50-95 while maintaining 2.9 M parameters, 22.8 GFLOPs, and 127 FPS under the current experimental setup.
Virtual metrology (VM) is widely used to infer wafer quality from equipment and process data, but its industrial value often deteriorates after preventive maintenance, chamber cleaning, recipe migration, or tool transfer because predictor-centric models indicate degraded accuracy without revealing which hidden process factor has changed. This paper proposes intervention-anchored hidden-state virtual metrology (I²S-VM), which uses naturally logged fab events as weak supervision to decompose latent dynamics into tool-state, recipe-state, and wafer-level components for joint metrology prediction and actionable state attribution. The framework combines sequential encoding of fault detection and classification (FDC) traces, intervention-aligned transition learning, cross-tool state-swap consistency under matched recipe context, and self-supervised multivariate time-series learning under sparse metrology. A population-level structural analysis suggests that, under selective interventions and sufficiently rich matched pairs, the learned decomposition is recoverable up to block-wise invertible transformations. Experiments on a confidential industrial epitaxial growth dataset from a German semiconductor manufacturer, containing 24,960 wafers, 4,320 labeled wafers, four tools, and eight chambers, show that I²S-VM achieves 1.24 Å MAE and 1.69 Å RMSE in the seen-tool/seen-recipe setting and consistently outperforms strong baselines in post-maintenance recovery, low-shot recipe adaptation, and zero-shot cross-tool transfer. These results indicate that intervention-anchored hidden-state learning can make VM not only more accurate but also more actionable for maintenance recovery, recipe qualification, and sister-tool deployment.
Accuracy of Virtual Metrology (VM) models, selection of wafers for physical metrology, and VM model adaptation are all vital areas of semiconductor manufacturing research which share a complex interdependence between each other. These interdependencies dictate the need for a unified framework which addresses VM modeling, uncertainty-aware selection of wafers for physical metrology, and adaptations of that model based on the newly obtained physical metrology results. In this paper, we propose a linear Gaussian dynamic model-based framework which models and tracks the behavior of VM model parameters over time, quantifies the uncertainty of VM model parameters and the VM model itself, and provides a theoretical framework for optimization of the selection of wafers which need to be physically inspected. We demonstrate the efficacy and superiority of this integrated VM modeling and upkeeping framework over the existing heuristic solutions using a uniquely large dataset obtained from an industrial plasma etch process performed on 114,774 wafers in a major 300 mm wafer semiconductor fab.
This paper investigates the mitigation of dopant deactivation in heavily phosphorus-doped silicon via phosphorus-nitrogen co-implantation. Dopant-vacancy complexes formed during sequential thermal processes are responsible for a reduction in carrier concentration, thereby narrowing the thermal process window. Nitrogen preferentially binds vacancies relative to phosphorus. Therefore, co-implantation suppresses the formation of phosphorus-vacancy complexes. Hall measurements show reduced deactivation in co-implanted samples. FTIR identifies features consistent with N2V2 formation at higher annealing temperatures. Raman spectroscopy shows reduced intensity of the 520 cm-1 c-Si peak in co-implanted samples, consistent with a degraded crystallinity and reduced mobility. SIMS shows broader phosphorus profiles after the second anneal, with slightly greater broadening in co-implanted samples, and a mid-depth nitrogen signal drop attributable to matrix effects on ion yield. TEM images show additional near-surface dark-contrast features in the co-implanted samples, qualitatively consistent with residual defects or local strain fields. These results indicate that nitrogen co-implantation mitigates deactivation under practical thermal budgets, albeit introducing a trade-off in carrier transport due to impurity/defect scattering.
Semiconductor manufacturing data sharing is constrained by intellectual property (IP) concerns, which makes it difficult to apply collaborative learning even when multiple installations of the same equipment exist. This paper studies the applicability of adversarial variational autoencoders (VAE) as a practical sanitization mechanism for this setting. Sensitive process variables are specified by a domain expert, and the model is trained to preserve utility while making those variables harder to infer from the released representation. We evaluate the approach on native semiconductor manufacturing time-series runs, first in the original single-party setting and then in a small multi-peer extension with local and joint adversaries. The results suggest a privacy-utility trade-off: sanitized representations retain the main public operating regimes while degrading reconstruction of the protected variables. The distributed study further shows that leakage must be evaluated after aggregation, not only per peer. These results position adversarial VAE sanitization as a useful applied tool for semiconductor data sharing, while also highlighting the limitations of the current centralized simulation and small number of available runs.
Semiconductor Fabs consume substantial amounts of energy, mainly in the form of electric power, to operate manufacturing equipment and to rigorously control the environment in the Fab. Heating and cooling of the cleanroom and the equipment is a significant part of the energy demand. We have found opportunities to reduce the demand by carefully calibrated changes of two systems, the control of relative humidity (RH) in the cleanroom and the way in which we supply cooling water to the equipment. Varying these conditions can lower energy consumption and cost, but it can also affect the production process in a number of ways. To avoid adverse effects we established a list of potential issues and a plan to prevent any deviations. We then varied RH in a controlled fashion and verified that production can continue without issues. A similar approach was used to make a change to the cooling water supply. By equalizing the temperature between two separate systems used across tool platforms and then connecting these systems we gain efficiency, reduce complexity and save energy. As with the humidity change the challenge is to ensure there is no impact across all equipment affected by the change. We achieved a significant reduction of energy consumption through these changes.
The accuracy of the resonant frequency directly determines the fundamental performance and application value of the microelectromechanical systems (MEMS) resonator. However, current methods exhibit inherent limitations, including the cumbersome and time-consuming nature of finite element simulation techniques, as well as the difficulty of traditional machine learning methods in effectively learning physical laws during prediction, which may lead to results that contradict established physical principles. This paper proposes a physically constrained dual-channel neural network framework (PhyC-DCF), which aims to address the issue of prediction results contradicting physical principles by embedding physical prior knowledge, providing an efficient and accurate resonant frequency prediction tool for MEMS resonators. PhyC-DCF comprises a target resonant mode channel and an auxiliary resonant mode channel, which predict their respective resonant frequencies. The auxiliary channel integrates target features through resonant mode coupling mechanism, enabling complementary feature learning. Subsequently, a hybrid loss with physical constraints exploits resonator physics to guide training. The PhyC-DCF not only reduces error metrics but also effectively suppresses physically inconsistent phenomena such as frequency inversion, thereby providing an efficient and reliable computational tool for resonator design.
In the integrated circuit manufacturing process, the wafer profile control in the copper chemical mechanical planarization (Cu CMP) exhibits higher uncertainty compared to oxide chemical mechanical planarization, primarily due to the predominant influence of chemical reactions rather than mechanical friction. Real-time monitoring of copper film thickness using eddy current technology is an effective method for ensuring the accuracy of polishing pressure feedback adjustment system in CMP process. However, the edge effect causes attenuation of the eddy-current signal, distorting the measurement of wafer edge thickness and increasing the risk of residual defects in Cu CMP. The objective of this study is to investigate the mechanism of eddy current edge effect through numerical simulation and online experiments, and propose an optimization methodology applicable in IC manufacturing. The key factors that were evaluated include the coil and ferrite structure, excitation frequency of the eddy current sensor, position of wafer radius, thickness of copper film, and kinematic relationship between sensor and wafer. A compensation coefficient matrix is proposed to optimize measurement distortion caused by the edge effects. The feasibility and accuracy of this method have been verified in the practical application of the Cu CMP process.
