On-chip SRAM protection has become a fundamental requirement in modern secure Systems-on-Chip (SoCs), driven by increasingly stringent low-power reliability and security standards. To counter Volt Boot and Cold Boot attacks, recent defenses predominantly rely on True Random Number Generator (TRNG)-driven address and data (de)mapping schemes designed for resource-constrained environments. However, such uniform TRNG-based XOR mapping mechanisms, are intrinsically vulnerable to optimization-based cryptanalysis due to their inherent linearity. In this paper, we present a chosen-plaintext attack based on Particle Swarm Optimization (PSO) that exploits this linear structure to recover protected memory contents. Across nine experimental configurations with key sizes ranging from 128 to 512 bits, the attack achieves complete memory recovery with perfect reconstruction accuracy ($N M S E=\mathbf{0}$ and $S S I M=\mathbf{1. 0}$). Moreover, the effective search space is reduced by up to $\mathbf{1 0}^{147} \times$ compared to exhaustive brute-force exploration, underscoring the practical insecurity of linear XOR-based TRNG mapping schemes. To mitigate this vulnerability, a group-based SRAM address and data (de)mapping architecture is introduced that disrupts global linear dependencies while preserving standard access latency. The experimental results demonstrate a substantial degradation in the effectiveness of the attack, obtaining NMSE values in the range of 0.117 to 0.279 and $P S N R$ between 5.54 and 9.30 dB, corresponding to approximately 99.7% corruption of the reconstructed data. The proposed countermeasure achieves this enhanced security with negligible hardware cost, incurring less than 0.4% area overhead.
Hyperdimensional Computing (HDC) is a neuroinspired paradigm ideal for hardware acceleration that is resilient to noise and faults. Despite this potential, the literature on fault analysis in HDC has focused almost exclusively on associative memories, overlooking the functional units of the accelerator itself. To address this gap, this work investigates the vulnerability of a custom open-source HDC hardware accelerator through transient fault injection-not within the associative memory, but in the functional units responsible for hypervector processing. Our fault injection campaigns, using simulation and real proton injection, show that higher hypervector dimensionality improves fault tolerance in data, even within the accelerator. However, control and addressing signals are more susceptible, leading to permanent write errors.
Efficiently storing memory test outcomes by preserving exact failure information in Automotive Systems-on-Chip is currently one of the major test challenges. Due to the limited availability of the on-chip buffer memory and the non-negligible time needed to transmit test results, their exact failing coordinates may be wasted due to the buffer saturation. To overcome this limitation, an efficient approach is to compress the detected faults using on-chip test resources, enabling the tester to retrieve the fault information at the end of the memory test. Although this method achieves significant memory savings, it does so at the cost of losing the exact failing bitmap coordinates, thereby introducing a lossy compression effect. To solve this issue, this paper proposes a framework relying on super-resolution (SR) artificial intelligence models to reconstruct off-chip, with high accuracy, the failing bitmaps. On-chip 256x256 coordinate-based failing bit test results are saved in a compressed format using $16 \times 16$ bitmaps. This compressed diagnostic information is then fed off-chip to the SR framework to return very accurate fullchip predictions on $256 \times 256$ bitmaps. As a case of study, the developed SR model has been trained on a dataset composed of real industrial failing RRAM results, achieving 98% accuracy. Overall, the off-chip proposed methodology achieves high global SR scores: competitive metrics adopting Structural Similarity Index Measure (SSIM) have been used, and all return results above 98% accuracy of reconstruction.
Interest in Near-Memory Computing (NMC) architectures continues to grow due to their ability to reduce data movement between processing and memory units, improving latency and energy efficiency. Beyond this, the computation capabilities available in the NMC logic layer open a new and unexplored opportunity to exploit these resources for memory testing at lower cost. This work introduces a fully programmable Finite State Machine (FSM)-based MBIST solution dedicated to NMC architectures. By supporting multiple test algorithms, it enables flexible fault coverage for both production testing and in-field diagnostics. The key novelty lies in reusing existing NMC logic layer resources to reduce BIST hardware overhead while leveraging NMC parallelism to accelerate test execution. Simulation and synthesis results show that, for a $\mathbf{1 K B}$ case-study NMC architecture, the implementation requires only 5.7% hardware overhead and achieves a $9.5 \times$ speedup over a CPUbased approach while preserving full algorithmic flexibility.
RISC-V is increasingly considered a strategic architecture for technological sovereignty and long-term platform independence, yet its practical maturity across software, performance and security is still debated. This paper presents an integrated, hardware-grounded assessment of the current RISC-V ecosystem. We first analyze software readiness by examining toolchain fragmentation, operating-system integration, and deployment effort across commercial ASIC boards and configurable FPGA soft-cores. We then benchmark representative processors using CoreMark, Geekbench 6, and SPEC2017, and contextualize the achieved results through direct comparison with contemporary ARM and x86 systems. Finally, we evaluate susceptibility to Transient Execution Attacks on three prominent open-source cores (BOOM, NOEL-V, and CVA6). The results show a clear three-way trade-off. Software support remains heterogeneous: ASIC platforms provide faster bring-up, whereas soft-core deployments require substantial hardware-software codesign effort. From a performance perspective, the best evaluated RISC-V ASIC demonstrates competitive per-cycle efficiency for embedded-class workloads, but a significant gap persists versus high-end proprietary processors; on FPGA soft-cores, low frequency and memory-system constraints often prevent completion of demanding benchmark suites. From a security perspective, all evaluated open-source cores are vulnerable to a subset of transient-execution attacks, with broader attack surfaces associated with more aggressive speculative microarchitectures. Overall, RISC-V is already a deployable opportunity for customizable embedded domains. For high-performance, general-purpose use, closing the gap requires coordinated ecosystem consolidation and rigorous security-by-design co-validation across hardware and software layers.
