As CMOS scaling extends beyond gate-all-around (GAA) nanosheet (NS) transistors, the complementary field-effect transistor (CFET) is a leading candidate for sub-1-nm nodes. To date, no open-source process design kit (PDK) is available to support a complete register-transfer-level (RTL) to GDSII flow on a CFET device architecture, making design-technology co-optimization (DTCO) impractical for academic researchers. This work introduces MATRIX-A5, an open-source predictive sequential-CFET PDK for pathfinding at the A5 node, which allows a full RTL-to-GDSII flow in a commercial EDA eco-system. Five sequential-CFET standard-cell libraries, benchmarked against a GAA nanosheet baseline library, cover the design freedom that sequential CFET provides, including independent NMOS and PMOS nanosheet sizing, and a CFET-flexible (CFlex) track-mixing methodology mixes nanosheet widths at a common row height or across hybrid row heights. A RISC-V core and systolic array taken through the full flow across the libraries quantify how each sequential CFET DTCO choice trades off among area, power, leakage, and frequency metrics.
In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration of static/dynamic kernels for transformers and context-switching workloads, while realizing efficient floating point (FP)/integer (INT) compute-in-memory (CIM). With full-stack, cross-layer co-designs, we present the first complete mixed-signal physical design implementation of an OS-on-CMOS 3D-integrated circuit (IC) with 32.9 TOPS/W energy efficiency and 102.4 TOPS/mm2 compute density. The post-3D-layout simulations calibrated with device experiments demonstrate that the 3D-NVGC LLM accelerator delivers a $52.3\times $ gain in holistic system efficiency over planar CMOS-based and a $3.2\times $ gain over 3-D dynamic random-access memory (DRAM)-based solutions, respectively.
Next-generation scientific instruments in high-energy physics, X-ray imaging, fusion diagnostics, and other data-intensive applications generate data rates that increasingly exceed practical communication bandwidth and power budgets, making the traditional approach of transferring raw data to remote computing systems unsustainable. This paper presents the Vertically Integrated AI for Sensing and High-Performance Computing (VIAS) project, which treats three-dimensional heterogeneous integration not merely as an advanced packaging technology but as a computational design paradigm that jointly shapes algorithms, hardware architectures, and memory organization. Rather than focusing on a single accelerator, VIAS explores a diverse set of AI and HPC workloads, including compact neural networks, spiking neural networks, hyperdimensional computing, vision transformers, machine-learning-based compression, and modular chiplet accelerators, to demonstrate how vertically integrated architectures reduce data movement through algorithm–architecture–technology co-design. Across these case studies, we identify recurring design principles that exploit dense vertical interconnects, memory locality, and specialized heterogeneous compute engines to enable real-time processing directly at the detector edge. We further discuss the common system-level challenges, including thermal management, memory hierarchy, communication, and 3D-aware design automation, that must be addressed to realize future intelligent scientific instruments. Together, these efforts establish a reusable co-design methodology for next-generation edge-AI and HPC systems built around vertically integrated heterogeneous architectures.
Probabilistic computing and uncertainty-aware inference require hardware-efficient generation of stochastic activations. This paper presents a CMOS-MRAM stochastic neuron in which stochasticity is encoded into programming-pulse distributions rather than relying exclusively on the intrinsic stochastic switching dynamics of the MRAM device. The nonlinear switching boundary of the SOT-MRAM acts as a compact probabilistic comparator that translates stochastic pulse-width and pulse-amplitude combinations into Bernoulli-distributed neuron activations. Independent modulation of programming-pulse parameters enables the implementation of hundreds of programmable stochastic transfer curves using a single Bernoulli random source. Unlike deterministic neurons that explicitly evaluate activation functions, the proposed neuron directly generates Bernoulli-distributed activation samples through stochastic switching attempts. Circuit-level simulations demonstrate that the complete implementation requires 1175 transistors while consuming 0.77 pJ per stochastic output bit with approximately 20 ns latency (50 Mbit/s). The proposed neuron was evaluated using a quantized MNIST inference framework to investigate the impact of programmable stochastic transfer curves on classification performance under multiply-accumulate (MAC) variability. Adaptive selection of the transfer curve maintained classification accuracy near 90% across MAC variability levels from −40% to +40%, recovering approximately 35% absolute accuracy under the severe −40% variability condition. Beyond classification, repeated stochastic inference naturally enables uncertainty estimation by measuring the predictive entropy of the resulting class distribution. Using out-of-domain rotated MNIST inputs, the mean normalized predictive entropy increased from 0.104 to approximately 0.27 as classification accuracy degraded from 90.5% to nearly 10%. Confidence-based filtering further improved the accuracy of retained predictions, demonstrating a strong correlation between uncertainty estimates and prediction correctness. These results highlight the potential of CMOS-MRAM co-design for compact, energy-efficient, and uncertainty-aware probabilistic neural network hardware.
