SiC strained nMOSFETs with sub-35 nm gate length can realize superior f T above 400GHz attributed to more than 20% enhancement of the mobility and transconductance. This super-400 GHz f T makes SiC strained nMOS a premium device for mm-wave CMOS circuits design. However, the SiC nMOSFETs reveal a dramatic increase of flicker noise and random telegraph noise (RTN), which may cause worse phase noise and detrimental impact on CMOS oscillator stability. The complex RTN features abnormally long capture and emission time constants (τ c and τ e ) and suggests new mechanism responsible for the anomalously slow trapping and detrapping, due to a significant increase of the relaxation energy from SiC strain. This critical trade-off between high frequency performance and low frequency noise should be considered seriously for an appropriate deployment of high mobility devices and optimization adapted to RF and analog circuits.
Designing lightweight convolutional neural network (CNN) models is an active research area in edge AI. Compute-in-memory (CIM) provides a new computing paradigm to alleviate time and energy consumption caused by data transfer in von Neumann architecture. Among competing alternatives, resistive random-access memory (RRAM) is a promising CIM device owing to its reliability and multi-bit programmability. However, classical lightweight designs such as depthwise convolution incurs under-utilization of RRAM crossbars restricted by their inherently dense weight-to-RRAM cell mapping. To build an RRAM-friendly yet efficient CNN, we evaluate the hardware cost of DenseNet which maintains a high accuracy vs other CNNs at a small parameter count. Observing the linearly increasing channels in DenseNet leads to a low crossbar utilization and causes large latency and energy consumption, we propose a scheme that concatenates feature maps of front layers to form the input of the last layer in each stage. Experiments show that our proposed model consumes less time and energy than conventional ResNet and DenseNet, while producing competitive accuracy on CIFAR and ImageNet datasets.
As a new coding tool of Versatile Video Coding, Luma Mapping with Chroma Scaling (LMCS) maps luma samples and scales chroma residuals based on the mapping function to improve video quality and compression ratio. To achieve real-time decoding and improve the throughput, a hardware decoder needs to be developed. In this paper, a high throughput LMCS hardware decoder design was proposed. Three separate modules were designed to realize the LMCS processes with two implementation schemes of the Luma Mapping module discussed and the better one used. The proposed design reached 535 MHz at 28nm technology, capable of processing videos at 4K@120fps.
The angular displacement sensor is a sensing tool used to detect angle, angular velocity, and angular velocity by converting the amount of angular displacement into an electrical output. Photoelectric encoders, which are currently utilized extensively in engineering practice, have many benefits over other types of angular displacement sensors, including high precision, high durability, small size, wide measuring range, and ease of installation. In this study, a photoelectric chip based on a dual code channel hybrid readout circuit for a high precision Photoelectric encoder is constructed. The circuit uses a single pseudo-random code element that corresponds to a single light and dark stripe of the incremental code mechanism. It can read absolute position information directly within the tolerance of a code plate engraving error of no more than a quarter cycle, and it can also perform sampling at a rate of 1MS/s while maintaining a resolution of 22 bits. The pseudo-random code channel generates two inverse pseudo-random codes using two separate photodetector arrays, which are then passed through two amplifiers and connected to a comparator for comparison. The result is a 1-bit digital signal as the code channel's final output. A 1-bit digital signal is the output's ultimate form. The device is 4.6mm by 3.5mm and uses a 0.35m CMOS technology.
As a highly repetitive logic operation unit in programmable logic modules, the operating speed of a carry adder circuit is crucial to the overall performance of the programmable logic circuit. In order to optimize circuit propagation delay and area overhead, this paper proposes an improved design scheme for carry adder circuits. Firstly, several basic adder structure types and their performance characteristics are compared to determine the most suitable architecture for carry adder circuits in programmable modules. Then, based on the carry-propagate principle of the carry lookahead adder, a novel single MOS transmission gate structure is proposed to optimize the underlying carry logic circuit. Finally, the carry adder circuit is implemented using a full-custom design flow in TSMC 28nm technology. Experimental results show that compared to existing logic designs, the proposed carry adder circuit in this paper reduces propagation delay and area overhead by 14% and 26.5% respectively.
