Interposer-based multi-die FPGAs (2.5D) are composed of multiple dies interconnected externally via wires, allowing the creation of FPGA systems with increased capacity. These external connections are generally fewer than the die's internal interconnection network and contribute to a higher delay and wirelength. These architectural limitations must be considered while optimizing PnR tools for multi-die solutions. The configuration of the interposer interface plays a crucial role in determining the routing resource availability at the die boundary and in ensuring congestion-free solutions. Interposer wires are generally designed to be thicker than the wires in the die's internal interconnection network, and their length can significantly impact overall delay. Longer interposer wires allow longer strides across the die, reducing the need for additional internal routing resources to handle cross-die net routing. Given these conflicting factors, it is crucial to determine an optimal length for the interposer wires. In this study, we aim to investigate how the length of the interposer wire influences the overall performance of PnR tools. We have developed a multi-die placer, LiquidMD and router, CRouteMD capable of accommodating various interposer lengths and have analyzed the impact of interposer length on the quality of PnR. Using a flexible interposer interface based on Xilinx's Virtex-7 architecture, we investigated wire lengths ranging from L12 to L48. In our comparison of PnR results across various interposer wire lengths, ranging from L12 to L48, we found that an optimal interposer wire length of approximately 14% of the die height (L30) improves the overall routing performance. This length of interposer wire reduces the CPD by 5% as compared to the longest interposer wire length which covers 22% of the die height.
Clustering is a critical step in VLSI design. Good clusters can aid in partitioning, floorplanning, and netlist reduction. In this work, we adopt a data mining technique to extract modular clusters and networks between clusters from placement evolution. We observe that state-of-the-art analytical placers propagate standard cells as Modular Clusters during placement evolution. And other noisy cells, which cannot be assigned to a specific cluster, form a network structure called Inter-Cluster Networks (ICNs). We propose Cascade HDBSCAN to extract Modular Clusters at different granularity as well as Inter-Cluster Networks in placement evolution. And we reveal Modular Clusters and Inter-Cluster Networks adhere to different Rent's rules. Furthermore, we provide a detailed analysis on the clustering structure and demonstrate VLSI netlists are small-world networks. Modular Clusters are localized groupings connected by Inter-Cluster Networks that function as shortcuts in the networks.
Moore's Law has been guiding the development of the VLSI industry for the past half-century. This law underscores fabrication technology's crucial role in enhancing chip performance. However, with technology nearing physical limitations, we envisage that there is still significant potential for optimizing interconnection complexity in VLSI design. Interconnection complexity is characterized by Rent's Rule and the Rent exponent. We propose a new recursive normalized approach that can measure the Rent exponent accurately by eliminating the imbalance between blocks of different sizes. Then we demonstrate that optimizing the Rent exponent of the FPGA netlist can yield substantial benefits throughout the CAD flow process, particularly in physical design. By employing the GNL synthetic netlist generator to control interconnection complexity, we observe that a lower Rent exponent results in reduced running time, total wirelength and area usage. We also include real-world circuits from the Koios 2.0 benchmark suite in our analysis. The run-time of packing, placement and routing are ranging from exponential to double-exponential with respect to the Rent exponent. Our study highlights the significant impact of interconnection complexity on the EDA physical design flow. The results suggest that optimizing the netlist's interconnection structure during logic synthesis or packing to reduce complexity could enhance the efficiency and performance of the EDA flow.
Electronic Design Automation (EDA) for Field Programmable Gate Arrays (FPGAs) strives to optimize the timing properties of physical circuits on FPGAs. The process involves logic synthesis and packing in physical synthesis, which generates a circuit graph. This graph is subsequently placed and routed onto the FPGA architecture to create a physical circuit. Researchers have demonstrated that merely minimizing circuit size does not necessarily lead to an optimal wirelength. Namely, as circuit size decreases the interconnection complexity can (and normally does) increase. This work focuses on gaining a better understanding of this phenomenon. We investigate the trade-off between size and interconnection complexity by examining ideal circuit graphs which are an abstraction of real circuits graphs based on Rent's rule. An ideal circuit is reduced to only three parameters: size Bc, interconnection complexity r and terminals per block K. First we study the effect of size Bc and interconnection complexity r on wirelength by making a visual representation with Donath's wirelength prediction method. The created visual clearly exposes and provides insight in the tradeoff between size and interconnection complexity. Furthermore, it shows that interconnection complexity is limited subject to circuit size. Second, we derive the shape of ideal circuit graphs based on its three parameters. We use the hypervolume-hyperarea interpretation of Rent's rule as a basis for constructing ideal circuit graphs. In understanding the structure of ideal circuit graphs it becomes clear why complexity is bound by size. We find that the complexity r of an ideal circuit is lower than log3(Bc)−1/log3(Bc). The model for building ideal circuit graphs enhances our intuitive understanding of interconnection structure in FPGA circuits and might be the basis for a new synthetic benchmark generation technique.
Interposer-based multi-die FPGAs comprise multiple dies interconnected externally via wires, enabling the creation of FPGA systems with greater capacity. These external connections are fewer in number than the internal interconnection network of a die and they also contribute to increased delay and wirelength. These architectural shifts necessitate placement and routing tools to strategically reduce the count of signals at the die boundary. Multi-die FPGA systems also offer substantial potential for design modularity, where each die can be optimized for specific functionalities. Adapting EDA tools to leverage these inherent device characteristics is imperative. Additionally, the modular nature of the system paves the way for parallelized implementations. Previous studies on multi-die FPGA placement have primarily concentrated on reducing signal crossings across die boundaries via global optimization. This strategy, however, incurs significant runtime demands, as it treats the multi-die FPGA as a unified fabric. This study presents a new methodology to partition and parallelize placement within a multi-die architecture. Our approach facilitates the optimization of partitioned nets without the reliance on a global optimization step. With netlist partitioning and adding virtual anchor blocks, the subcircuits can be placed on each die in parallel. The multi-die placer algorithm is integrated into the fast analytical placement tool 'Liquid'. A comprehensive performance comparison of our multi-die placer with the single-die monolithic implementation unveils similar quality results with improved runtime efficiency. Lastly, we compare our strategy to the widely-used academic placer, VPR, which relies on global optimization. The results demonstrate a 42x enhancement in runtime for lower estimations of Total Wire-length (TWL) and Critical Path Delay (CPD).
