Thickness scaling of FeFETs with Hf 0.5 Zr 0.5 O 2 (HZO) from 11 down to $4.6\mathrm{~nm}$ is systematically studied in this work in terms of the memory characteristics and the memory window (MW) narrowing mechanism. The HZO thickness scaling leads to low-voltage operation, higher $I_{\text{on}}/I_{\text{off}}$ ratio, lower S.S., and better endurance. It is also found, for the first time, that with reducing cycling voltage the dominant narrowing mechanism changes from MOS interface degradation to ferroelectric fatigue, which can be recovered by a high-voltage pulse. Based on this finding, we propose and demonstrate a method to improve endurance by utilizing this recovery, which is more effective in thinner HZO FeFETs.
The large memory window of $1.8\mathrm{~V}$ at the low write voltage of $2\mathrm{~V}$ is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge 0.98 Si 0.02 FeFETs with the channel phosphorus concentration larger than $1\mathrm{E}18\mathrm{~cm}^{-3}$, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of $\gt 1\mathrm{E}4$ seconds, linearly extrapolated 10 years, and high endurance $\gt 1\mathrm{E}11$ cycles are also demonstrated. The thermal budget is as low as $400^{\circ}\mathrm{C}$. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the $2\mathrm{~nm}$ node and beyond.
It is presented the first active-matrix (AM) mini light-emitting diode (LED) driver system for a back-light unit (BLU) that uses a newly proposed 1-pair clock-embedding unified standard interface (USI-B) to reduce EMI and power consumption. The system consists of a pixel driver IC (PDIC) and a pixel IC (PIC). The PDIC transmits 20-bit brightness data to the PIC to control the mini-LEDs. The USI-B, based on clock and data recovery (CDR), has been applied to enhance high-level noise tolerance, long-distance transmission, and EMI reduction. Self-current calibration and offset cancellation in the PIC allow for current accuracy of up to ±1% between PICs. This system can support 16,128 LED local-dimming zones (LDZ) using two PDIC and has a measured EMI level of less than 30dB($\mu$V/m). The PDIC and PIC were fabricated using a 65nm and 130nm CMOS process, respectively.
U-MRAM, an enabler of a diode-selected cross-point MRAM array, is demonstrated using a mature device structure identical to STT-MRAM. U-MRAM exploits the probabilistic switching of thermal fluctuations using a single write voltage. The asymmetric synthetic antiferromagnetic layer (SAF) enables promising UMRAM properties, including low voltage (0.6 V), high speed (10 ns), excellent endurance (>$10^{10})$, and long retention (>10 years) without an external magnetic field. Diode-selected U-MRAM is a strong candidate for future high-density embedded memory.
PowerVia Technology [1] is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of >90% in large areas of the core while showing >5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.
