voltage AlGaN/GaN HEMTs were designed for 160 V operation by systematically varying gate and access-region parameters. The selected design delivered an output-power density of 35 W/mm at 160 V, confirming the high-power capability of the technology. Measurements across the cofabricated 45 V reference and 160 V populations show substantial wafer-to-wafer and within-wafer variability at 160 V that is largely absent at 45 V, with the relative spread of output power growing from approximately 3% to 20%. Propagating the measured parameter spreads through the load-line relation indicates that this amplification is primarily carried by a device-to-device dispersion of the large-signal effective knee voltage, while the saturation current spread is approximately 2%. The saturation current is nonetheless identified as the strongest single predictor of output power because it is strongly associated with the underlying epitaxial and device quality that influences channel charge, transport, and high-field swing loss. An analysis directly correlates the pre-fabrication sheet density Ns, the post-fabrication maximum drain current IDSS,max, and saturated Pout. In the pulsed-IV subset, ΔRON retains a significant partial association with Pout. It is shown that manufacturability, rather than peak RF output capability, is the primary limitation for scaling GaN HEMTs toward higher voltage RF power operation.
With the increasing demand for high-reliability requirements, modern on-chip electrostatic discharge (ESD) protection designs must additionally account for microsecond-level Surge events, making the transient robustness of back-end-of-line (BEOL) interconnects a critical design consideration. Accordingly, a transmission line pulse (TLP) system and a Surge tester are utilized in this study to investigate the pulse-duration dependence of failures among the metal lines, vias, and contacts fabricated in a 0.18-μm CMOS technology. Distinct thermal responses and failure signatures are observed under TLP and Surge stresses. Experimental results have demonstrated that while transient current capability primarily was scaled with metal width, increasing the metal length will introduce a contrasting effect and slightly reduce the TLP failure current while marginally enhancing Surge capability at longer metal lengths. Furthermore, explicitly extracted minimum normalized current capabilities are provided to facilitate the robust layout sizing of global ESD metal buses and local protection devices for IC designers to well optimize their on-chip ESD protection design with layout consideration on all interconnection BEOL layers.
Process development in AMOLED manufacturing involves complex trade-offs between device performance and production economics under tight manufacturability constraints. Conventional process optimization approaches often rely on experience-driven parameter tuning or focus on isolated technical objectives, making it difficult to achieve systematic and reliable decision-making in high-dimensional and uncertain process spaces. In this paper, we propose a multi-objective modeling and optimization framework for joint performance and economic optimization in AMOLED manufacturing processes. The framework adopts a hierarchical parameter–performance–economics modeling structure to explicitly capture the interactions between process parameters, device performance indicators, and manufacturing economic metrics. Probabilistic safety constraints and uncertainty-aware surrogate modeling are incorporated to ensure reliable optimization under process variability. A safety-constrained multi-objective optimization strategy with trust-region control is developed to balance exploration efficiency and decision stability. A historically grounded case study shows that the proposed approach can generate feasible Pareto-optimal process configurations, improve constraint feasibility and normalized economic indicators relative to unconstrained search, and produce interpretable performance–economics trade-offs, while yield becomes more conservative. The results indicate that uncertainty modeling and trust-region control improve search stability in this evaluation.
Diffusion models have achieved remarkable performance in image denoising through iterative reverse processes. However, conventional fixed-step inference assumes uniform noise levels, an assumption that is often violated in Scanning Electron Microscopy (SEM) imaging, where varying acquisition conditions lead to significant noise fluctuations. This mismatch may result in either residual noise or excessive structural smoothing. To address this issue, we propose a diffusion-based denoising framework that determines the reverse inference steps according to the estimated noise level of each input image. By analyzing the progressive denoising behavior of the diffusion process, we reveal a stable and approximately linear relationship between the effective noise level of the input and the optimal inference step. Based on this observation, a wavelet-based noise estimation method is employed to quantify the noise intensity, and a Noise-Step mapping model is constructed to guide the reverse diffusion process. Experiments on an industrial semiconductor SEM dataset demonstrate that our method significantly improves restoration stability compared with conventional fixed-step strategies, effectively balancing noise suppression and structural preservation. Furthermore, ablation studies show that weak denoising preprocessing during training can reduce noise uncertainty and enhance the robustness of the learned diffusion prior.
Solid particles or residue in the foreline of semiconductor-manufacturing tools pose a variety of operational problems and even hazards. To address these issues, this paper presents a computational-fluid-dynamics (CFD) model of the cleaning of a particle trap in the foreline. The CFD model considers the plasma region, the reactive flow downstream, and the etching of residues. The model predicts pressure drops and etch rates in good agreement with experimental data. Moreover, the model considers a complex 3D geometry and the simulations are fast enough to fit within a design cycle. Therefore, the model could be useful to enhance particle traps for the foreline and the cleaning of the foreline with plasma.
