An auxiliary-controlled dual-differential (AC-DD) delay cell is proposed for a multi-phase, four-stage ring voltage-controlled oscillator (RVCO) to support high-frequency operation. The AC-DD delay cell incorporates one PMOS and one NMOS cross-coupled pair where the PMOS pair operates as a latch, and the NMOS pair enhances the oscillation frequency. Frequency tuning is achieved through auxiliary inputs connected via PMOS transistors from the output terminals. This configuration enables precise frequency control and improved high-speed performance. Post-layout simulations were performed using a 65 nm CMOS technology with a 1 V supply voltage. At an operating frequency of 2.7 GHz, the AC-DD delay cell-based RVCO has a phase noise of –103.7 dBc/Hz and a power dissipation of 13 mW. Furthermore, it achieves a figure of merit (FoM) of –161.18 dBc/Hz, improving 6 dB over conventional RVCO design, highlighting its enhanced efficiency and performance.
Given the widespread applications and importance of matrix multiplication, it is necessary to adopt and design compute units efficiently. Multipliers are the core component in any hardware design for matrix multiplication applications. In this work, we look into the design of the multiplier unit and propose a component, inspired by Booth’s encoding, called MiniBit. Our MiniBit can be used to build various bit width sized MiniMac multipliers. We present a study on 4b4b, 8b8b, and mixed multiplier designs based on our proposed design, which can be used in applications with matrix multiplication. We establish that MiniBits can be used to build more elaborate designs to support various intricate logic.
This work presents a novel approach for approximate multiplier design for applications with error-tolerance capabilities based on pre-processing of input operands for energy-efficient implementation. The key idea is to reduce the bitwidth of operands to enable efficient multiplication operations. In this paper, 8-bit inputs are processed to 5 bits, and multiplication is carried out on this 5-bit operand, followed by appropriate shifting to minimize error and enable hardware-efficient multiplication. The efficacy of the proposed design is computed based on error and performance metrics. Furthermore, when employed inside Multiply-Accumulate unit, the LUT utilisation decreases by 24.4
This paper presents a resource-efficient hardware architecture for computing the exponential function using the IEEE 754 single-precision (FP32) format. The method employs a 32-state finite state machine (FSM) that performs a stepwise subtract-and-multiply process to approximate the function. Each state corresponds to a specific input subrange and stores the smallest number in its subrange along with its precomputed e^x value. Based on the exponent of the input number, the relevant state is selected and the input is reduced iteratively by the stored value of the state. At each step, the corresponding exponential is multiplied into a product accumulator. The remainder is passed to the next state, continuing until the desired precision is achieved. This approach eliminates large memory-based lookup tables, reducing hardware complexity and memory usage. Modular floating-point addition and multiplication units are integrated for accuracy and scalability. The proposed design maintains low relative error at higher precision levels with efficient area and power usage. At a precision of four decimal places, the implementation results in an average relative error of 0.0033
Transformers are the heart of natural language processing (NLP) and are used for ML applications. The architecture of the transformers is made up of stacking of the encoder and decoder layers. This paper proposes a VLSI architecture of hardware accelerator for such transformer models. This architecture supports a dimensionality of 512, which has a 512 × 512 matrix as an output for detection. In this architecture a memory module for positional encoding (POS) part consists of precomputed POS values of sine and cosine, which makes the architecture both hardware and energy efficient. To compute the soft-max function, a simplified soft-max function is deployed in both blocks, which takes fewer LUTs and an efficient matrix multiplication block is used to achieve a more efficient result and less computational power, reducing the area for this architecture.
