This work presents an temperature sensor designed in a 22 nm process, using the 22-FDX design kit for this purpose. This sensor utilizes the threshold voltage and carrier mobility dependence on the temperature for voltage conversion, covering a temperature range of 0 degrees C to 100 degrees C. A key contribution of this work is the exceptionally low error of +0.137 degrees C and -0.075 degrees C achieved after a simulated one-point calibration. In addition, this device achieves a temperature coefficient of -1.69 mV/degrees C in the whole temperature range. It also consumes 23.11 mu A from a 0.8 V DC supply and has an estimated die area of 5024.9 mu m(2) (based on the schematic), of which approximately 5000 mu m(2) correspond to two MOM capacitors. These capacitors are required for stand-alone measurement, but in real-life scenarios, part of this capacitance corresponds to the load capacitance seen when an ADC is connected to the sensor's output. This temperature sensor is suitable for high-accuracy on-chip applications, standing out for its trade-off between area, temperature range, power consumption, error and temperature coefficient.
This paper presents a Deep Learning-based method for fetal and maternal heart rate monitoring, specifically designed for efficient hardware implementation. The proposed approach minimizes computational load by eliminating the denoising and filtering stages. The abdominal electrocardiogram (aECG) signal is thus segmented into 100 ms windows, which are processed by a Convolutional Neural Network (CNN) suitable for real-time implementation on edge devices. This design enables low-latency, continuous heart rate monitoring during pregnancy, supporting fetal well-being assessment and early detection of anomalies. In addition to its suitability for real-time applications, the method can detect fetal arrhythmias, thus providing valuable clinical insights during prenatal care.
This work builds on a recent contribution from the literature to improve isolation on single-pole single-throw switches by introducing an additional transistor at the gate of the series devices in a series-shunt architecture implemented in an FDSOI process. This paper explores the effects of this extra transistor when used in single-pole double-throw switches implemented with RF CMOS transistors in a 130 nm SiGe technology over the 6-20 GHz range. The insights drawn from the post-layout simulations confirm improved isolation, albeit at the cost of higher area consumption, lower output power handling, and higher insertion loss. The overall performance is evaluated using a figure of merit that combines these parameters, showing that the series-shunt configuration offers the best trade-off, while the analyzed approach may be advantageous in applications with area-constrained designs or very high isolation requirements.
This paper presents a system for automatic classification of telecommunication signals using signal processing, multi-domain features fusion, and machine learning techniques. Our system achieves a 97.72% classification accuracy across a wide range of SNR values (-20 dB to 18 dB) using an over-the-air radio-frequency (RF) signals dataset, while maintaining a relatively low complexity (167k learnable parameters). We employ a comprehensive feature extraction methodology that combines time-frequency representations, wavelet transform coefficients, and frequency domain statistics which are processed through a multi-layer architecture. This work demonstrates a systematic approach to signal classification that balances accuracy, computational efficiency, and generalization capability, with potential applications in spectrum monitoring, electronic defense, and cognitive radio systems.
Robust transmission of underwater acoustic signals is essential for the development of Internet of Underwater Things (IoUT) applications such as environmental monitoring, marine exploration, and also for the underwater localization of mobile entities. Underwater localization systems require the emission of pre-coded and modulated acoustic signals, which must be stored in the designed hardware and transmitted with high accuracy and reliability. This work compares two FPGA-based architectural approaches for managing the reading and emission of acoustic encoded signals stored on a microSD card for transmission in underwater environments. On the one hand, a fully hardware implementation by using finite state machines (FSMs) is presented; on the other hand, a soft-core processor to manage SD card access. The comparative analysis of both implementations is focused on performance, resource usage, design complexity, and flexibility. Experimental results show that both solutions are functional for underwater acoustic applications, highlighting advantages and limitations for the design of underwater embedded systems that require robust data handling from microSD memory.
