Executing scan tests at very-low voltage is a long-known industry best practice to screen resistive latent defects and contribute to enabling < 1 Defective Part Per Million (DPPM) performance for Automotive products. To be effective, it is necessary for these tests to run at near the intrinsic low voltage capability of the silicon. Slowing shift and capture clocks are best practices deployed to overcome Very-Low-Voltage (VLV) test timing limitations, but there are other challenges. This paper discusses two activities that enabled true VLV testing in a single digit FinFET technology. The first discusses a design implementation in the General-Purpose IO pads that supported correct signal level shifting at VLV and avoided action of low voltage detect circuitry during VLV testing. The second describes a series of design of experiments to characterize the test instrumentation at VLV conditions and optimize settings to robustly execute the tests at VLV conditions.
At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.
As semiconductor technology advances, small delay defects (SDDs) have become a major concern in System-on-Chip (SoC) testing due to shrinking timing margins. Moreover, diagnosing SDDs is getting even more challenging due to their subtle impact on circuit timing and the existence of process variations. This paper presents an SDD diagnosis method integrating timing-aware fault simulation with injected delay selection and a mismatch-weighted (MW) score method to enhance diagnostic accuracy. Rather than relying on fixed delay values, the proposed method determines injected delays based on the slack of transition paths, generating multiple delay sizes to improve fault simulation resolution. The MW score calculation adjusts contributions of failures, enhancing defect ranking and mitigating process variation effects. Experimental results demonstrate that the proposed method significantly improves SDD localization and reduces the number of fault candidates, outperforming conventional approaches in both accuracy and efficiency.
Scan-Based Design-For-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITEfor design modifications. We show that LITEsignificantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions.
System Level Test (SLT) of compute products, such as processors, graphic cards, or AI accelerators, can stress critical components on the platform to their rated maximum performance and thermal envelopes. This at-speed test requires thermal management solutions compatible with the dense SLT environment, deployable at scale. Here we introduce the challenges of thermal management in SLT, parameters that affect thermal envelopes, using a case study of DDR memory. We present typical thermal management solutions used in a high-volume system test, their advantages and shortcomings, introduce liquid cooled solutions that can overcome them, and the functional benefits of using advanced liquid cooled DIMM solutions at scale in test factories.
