This work proposes a unified three-stage framework that produces a quantized DNN with balanced fault and attack robustness. The first stage improves attack resilience via fine-tuning that desensitizes feature representations to small input perturbations. The second stage reinforces fault resilience through fault-aware fine-tuning under simulated bit-flip faults. Finally, a lightweight post-training adjustment integrates quantization to enhance efficiency and further mitigate fault sensitivity without degrading attack resilience. Experiments on ResNet18, VGG16, EfficientNet, and Swin-Tiny in CIFAR-10, CIFAR-100, and GTSRB show consistent gains of up to 10.35% in attack resilience and 12.47% in fault resilience, while maintaining competitive accuracy in quantized networks. The results also highlight an asymmetric interaction in which improvements in fault resilience generally increase resilience to adversarial attacks, whereas enhanced adversarial resilience does not necessarily lead to higher fault resilience.
Artificial intelligence (AI) is boosting the development of complex functionalities in the automotive domain, paving the way for autonomous decision-making capabilities of vehicles. However, integrating such complex functionalities at the system level is challenging due to the short time to market with limited development, verification, and validation periods. Moreover, automotive applications require compliance with strict safety regulations, which demands effective strategies to ensure timely development while allowing thorough dependability evaluations. This work addresses the system-level reliability of automotive applications by proposing a strategy named TIARA (Two-step IntegrAted Reliability Assessment) to assess the impact of hardware faults (modeled as soft errors) on AI-based perception tasks. Our strategy allows for the exploration and evaluation of algorithms, driving controllers, and critical operational scenarios, considering the effects of faults affecting the hardware up to the vehicle level. To tame the huge computational complexity, TIARA first exploits a static analysis to estimate the fault vulnerabilities and identifies the most critical code blocks. Then, the most critical application blocks (susceptible to faults from hardware) are targeted to evaluate the fault's impact on the vehicle dynamics and determine their effect at the system level, combining perception, control, and driving features. Our experimental results, obtained on a test case corresponding to a Lane Centering Assistance application based on the YoloP model and under different driving scenarios, show the feasibility and effectiveness of the proposed approach.
Silent Data Errors (SDEs), which corrupt or alter data without immediate detection, are an escalating concern for chip manufacturers and data centers. These errors can lead to serious consequences, especially when corrupted data is used in critical computing tasks. Their subtle and elusive nature makes SDEs particularly challenging to detect and address. This paper investigates manufacturing defects, specifically resistive opens, that have the potential to induce SDEs. We focus on defects that are undetectable by traditional Boolean-based testing methods and cause small delays in circuit behavior. The study also examines the challenges posed by FinFET technology, which, due to its reduced geometries, increased susceptibility, and the use of complex multi-fin and multi-finger structures, exacerbates the risk of SDEs. Furthermore, we explore how real-life operation conditions—such as IR-drop, crosstalk, and temperature variations—can contribute to the emergence of SDEs. Our findings identify certain resistive open defects as potential sources of SDEs and provide insights that could inform the development of enhanced manufacturing tests to mitigate these errors. This research offers a pathway to improving the robustness of chip designs and testing methodologies, ultimately reducing the impact of SDEs in critical systems.
Nanosatellites have emerged as a viable alternative for space missions due to their adaptability, cost-effectiveness, and potential for data collection operations in Low Earth Orbit (LEO). However, high radiation exposure in LEO poses a significant risk, particularly to the reliability of embedded systems that are vulnerable to memory failures and critical data errors. This context creates the opportunity to develop solutions that ensure the integrity of data stored in memory, which is crucial for mission success and satellite reliability. To address these challenges, this paper presents a new, robust approach for error correction code (ECC) for memory systems used in space applications. The approach, namely NASCERR, is the result of a partnership between Brazilian public universities and the private sector, and aims to validate the ROBC (Robust On-Board Computer), an on-board fault-tolerant computer system for CubeSats. The approach was implemented in a SmartFusion2 M2S025 FPGA operating as an intermediary block (Man-in-the-Middle) between the processor and the SRAM memory system of the satellite. The approach is said to be self-tuning, by adjusting the error correction strategy transparently and on-the-fly, according to the type and frequency of errors detected in memory, in mission mode. Intensive simulation campaigns demonstrated the proposed approach presents high resilience, achieving 100% recovery rate in bit-flip occurrency, while guaranteeing high workload computational performance.
Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) have emerged as effective solutions for enhancing local security in digital devices, offering secure IC authentication and random cryptographic keys. Among the components used to implement these primitives, Ring Oscillators (ROs) play a pivotal role due to their simplicity, scalability, and ability to exploit process variability. However, the effectiveness of ROs is challenged by their susceptibility to various fault attacks that tamper with the working conditions. Among these attacks, ElectroMagnetic Fault Injection (EMFI) was underscored as a real threat to the RO frequency through harmonic locking. Therefore, this paper aims to explore the impact of voltage drop and temperature rise on the harmonic susceptibility of a RO under EMFI. Experiments involved deploying a grid of 4600 ROs across different FPGAs to highlight the increased intensity of harmonic errors due to the major effect of voltage fluctuations. Further EMFI campaigns with X-ray irradiation provided additional insights into the critical relationship between the RO frequency and its harmonic susceptibility to EMFI.
