This paper presents an exact fringe-capacitance modeling framework for parallel-plate structures based on Schwarz-Christoffel (SC) mapping and establishes the classical Kirchhoff formula as a benchmark for solver validation. Conventional 3D field solvers approximate edge singularities through mesh refinement, which can still leave systematic underestimation of fringe capacitance despite apparent numerical convergence. The proposed SC-based formulation treats the singular edge field analytically and provides an exact reference for quantifying residual extraction error. The resulting benchmark offers a physics-consistent validation framework for fringe-field modeling and parasitic estimation in edge-dominated structures.
The increasing demand for secure hardware systems has intensified the need to evaluate vulnerabilities against noninvasive attacks such as side-channel attacks (SCA), which can extract secret information without altering device functionality. Elliptic Curve Cryptography (ECC)-based algorithms are widely adopted due to their strong security and efficiency; however, ensuring their resilience at the hardware level remains a critical challenge. In this paper, we present a customized ECC-based ECDH hardware design incorporating a Karatsuba-based multiplication architecture optimized for efficient implementation. To assess security, a pre-silicon side-channel leakage analysis is performed at the RTL level using power trace evaluation and a t-score-based statistical framework. The results demonstrate that leakage is input-dependent and can be localized to specific stages of computation, particularly the initial stage of the design. Unlike conventional post-silicon approaches, the proposed methodology enables early-stage detection and localization of leakage-prone regions at the RTL level, providing actionable insight for targeted countermeasure integration and improved hardware security.
As the semiconductor industry pushes for faster design cycles and higher performance, ensuring long-term device reliability has become a critical challenge that traditional, time-consuming physics-based simulations struggle to meet. This creates an urgent need for data-driven modeling approaches that utilize artificial intelligence to enable rapid, reliability-aware circuit design.This study addresses this need by implementing machine learning techniques to model Hot Carrier Injection (HCI) degradation which shifts transistor characteristics over time in a 180 nm planar NMOS node. By utilizing experimental data recorded under controlled electrical stress, the research evaluates and compares the performance of two ensemble learning models: Random Forest (RF) and XGBoost (XGB) with similar studies. These ensemble methods work by combining the predictions of multiple decision trees to improve overall stability and precision.The models are systematically optimized to balance computational efficiency with predictive accuracy, using metrices such as percentage root mean square error (% RMSE) and $\mathbf{R}^{\mathbf{2}}$ score to track changes in threshold voltage and drain currents. The findings validate that AI-based modeling can effectively capture complex, non-linear aging trends in legacy nodes, providing a scalable foundation for integrating automated reliability assessment directly into Electronic Design Automation (EDA) tools.
Model order reduction (MOR) is essential for the efficient simulation of large-scale RLCk models arising in modern integrated circuits. Second-order formulations are particularly attractive for such models, since they preserve structural properties of the susceptance-based representation and enable passive reduced-order modeling. Among MOR techniques, second-order balanced truncation (BT) provides reliable error control and compact reduced-order models (ROMs), but its applicability is hindered by the high computational cost of solving largescale Lyapunov equations. In this paper, we introduce a lowrank second-order BT methodology based on multi-point rational Krylov subspace projection for reducing large-scale RLCk models. The proposed approach features a frequency-adaptive expansion point selection strategy and two effective convergence criteria, while reduction is performed through a congruence transformation to ensure passivity. Experimental evaluation on custom circuits designed in a 22 nm FDSOI technology indicates that the proposed method produces more compact and accurate ROMs than a conventional second-order BT approach, while significantly improving computational efficiency.
The high peak-to-average power ratio (PAPR) inherent in 5G and 6G OFDM-based modulation schemes forces power amplifiers (PAs) to operate close to their deep saturation limits. While this maximizes power efficiency, it inevitably triggers severe nonlinear distortion and hard clipping. Conventional digital predistortion (DPD) techniques, such as Memory Polynomials (MP), handle mild nonlinearities reasonably well. However, they struggle significantly under deep saturation unless equipped with high-order polynomial terms-a feature that consumes more digital signal processing (DSP) resources on field-programmable gate arrays (FPGAs). To tackle this hardware bottleneck, this paper introduces a resource-constrained DPD architecture based on an Augmented Real-Valued Time-Delay Neural Network (ARVTDNN). We deliberately constrained the feature extraction matrix, restricting the memory depth to $\mathbf{M}=\mathbf{2}$ and the polynomial order to $\mathbf{K}=\mathbf{3}$, thereby significantly reducing hardware complexity. We experimentally evaluated this neural network approach against a classical Least Squares-based MP (MP-LS) model, driving a GaN HEMT PA into deep saturation using a 100 MHz 5G OFDM signal. The results are positive. Thanks to its nonlinear activation functions, the neural network effectively compensates for the truncated feature space. Under the exact same stringent hardware constraints, the neural network DPD achieved a Normalized Mean Square Error (NMSE) of -44.04 dB and an Error Vector Magnitude (EVM) of 0.63%, outperforming the classical MP-LS model’s -40.09 dB and 0.99%. Ultimately, this demonstrates a highly robust, resource-efficient DPD solution suited for next generation wireless transmitters.
