True Random Number Generators (TRNGs) are fundamental modules in information security, whose performance directly impacts the reliability of cryptographic systems and security protocols. However, achieving an optimal balance between hardware resource efficiency and throughput in TRNG design remains challenging. To address this, this paper proposes a highly efficient TRNG scheme based on a nested architecture. By introducing a multi-level nested oscillatory network, the dynamic randomness and output complexity of the entropy source are effectively enhanced, significantly increasing the random bit generation rate. Experimental results show that the designed TRNG achieves a throughput rate of 1.1 Gbps on a ZYNQ-7010 development board and a further improved rate of 1.4 Gbps on an Artix-7 platform, while consuming only 13 LUTs and 4 DFFs in hardware resources, demonstrating excellent resource efficiency. Notably, the random sequences generated by the proposed TRNG have passed multiple statistical randomness tests, including NIST SP 800-22, TESTU01, NIST SP 800-90B, and AIS-31, validating the significant advantages of the proposed TRNG structure in terms of compactness and high throughput.

Physically unclonable functions (PUFs) are widely providing identity and foundational security services for billions of devices in the IoT era. However, the inherent linear additive model of arbiter PUFs (APUFs) is highly vulnerable to machine learning (ML) attacks. To address this issue, we propose an obfuscated arbiter PUF (OA PUF) based on the Lorenz attractor system. This system leverages the butterfly effect’s ability to amplify minute differences to obfuscate challenges, enhancing resistance against modeling attacks. The PUF’s core architecture employs a multimode clock network (MMCN) to extract fine-grained circuit characteristics and nonlinear circuit delay, generating responses. Based on the structural characteristics of PUFs, a highly secure authentication protocol is proposed. This work was implemented and evaluated on a field-programmable gate array (FPGA) hardware platform. Experimental results demonstrate robust resistance against four ML modeling attacks: logistic regression (LR), artificial neural networks (ANNs), support vector machines (SVMs), and covariance matrix adaptive evolution strategy (CMA-ES). Prediction accuracy for all attack types remained near 50%. Furthermore, the implemented PUF demonstrated outstanding performance across key metrics, with reliability, uniformity, and uniqueness approaching ideal values.

Existing IC tests face challenges of decreased testability and increased costs of Three-Dimensional Stacked Integrated Circuit (3D-SIC) and changes in the test flow. This paper proposes a low-cost built-in self-test structure based on reconfigurable Three-Dimensional Linear Feedback Shift Registers (LFSR). In pre-bond tests, LFSRs on each layer independently generate test patterns. In mid-bond and post-bond tests, the LFSRs of each layer, before bonding, are reused to connect the LFSRs of multiple layers and form a larger LFSR, thereby generating test patterns. Our method applies to all pre-bond, mid-bond, and post-bond tests, reducing the total area overhead. The structure complies with test standards and supports serial-parallel hybrid tests. Additionally, we present a test data compression method that combines threshold-compatibility compression with graded LFSR encoding compression. The compatibility threshold is set in the test pattern compatibility process to control the maximum number of deterministic bits of the test patterns after compatibility within the threshold range. The test patterns after compatibility are divided into multiple classes according to the number of deterministic bits. Different-sized LFSRs are constructed for each class to encode the test patterns into seeds of different lengths. The proposed test data compression method effectively reduces the amount of test data storage and test time. Our experimental results on the ISCAS’89 circuit indicate that, compared to non-reconfigurable BIST methods, the proposed method reduces test area overhead by 44.71% and reduces test data storage and test time by 98.31% and 82.35%, respectively.

Through-Silicon Vias (TSVs) are the key component in stacking three-dimensional chips. It is imperative to detect TSV faults during the manufacturing process. However, the high testing cost and difficulties in testing the entire TSV bonding process using the same structure are open challenges in the manufacturing process. This paper proposes a TSV testing procedure based on a reconfigurable ring oscillator structure. The reconfigurable ring oscillator (RRO) performs fault detection on TSVs Pre-bonding and carries out Mid-bond and Post-bond testing by reusing the technique Pre-bonding. The reconfigurable Linear-feedback shift register(RLFSR) can be employed for circuit testing and generate RRO control signals. Our simulation results of HSPICE substantiate that the proposed structure effectively detects faults at each stage of TSVs. Compared with the state-of-the-art testing techniques, the test data storage volume is reduced by 53.41% and 24.39%, respectively, and the area overhead is reduced by 42.33% and 19.87%, respectively.

Marginal manufacturing defects in advanced FinFET/GAA technologies can evade production test at nominal conditions yet trigger field failures and silent data corruption (SDC) under voltage/temperature stress. This paper proposes a stress-aware marginal-defect testing framework based on a Dynamic Critical Resistance Model (DCRM). DCRM characterizes the nonlinear critical-resistance boundary Rcrit(VDD,T) under an at speed launch/capture observation rule, capturing stress-induced boundary movement and defect pass-fail phase transitions. The extracted cross-condition boundaries are encoded into ATPG-consumable user-defined fault model (UDFM) entries, enabling a Coverage-Range-First ATPG (CRF-ATPG) strategy that greedily selects patterns to maximize coverage of the dynamic resistance-sensitive interval. Experiments on ten benchmark circuits across SAED-14 nm, TSMC-28 nm, and TSMC-65 nm show that CRF-ATPG consistently improves marginal-defect coverage (Cov2) over cell-aware ATPG while preserving hard-fault coverage (Cov1).

To address the energy-efficiency constraints of arithmetic units in high-fidelity image processing applications, a classified truncation compensation approximate Booth multiplier driven by constrained level selection (CLS) is proposed in this article. The proposed approach models low-weight partial-product contributions and realizes fixed-boundary truncation with input-dependent classified compensation to reduce hardware overhead while controlling truncation-induced bias. Based on the proposed method, three 8-bit approximate multipliers are implemented by combining approximate Booth encoders, approximate 4-2 compressors, and truncation-compensation schemes. Synthesis results in TSMC 90 nm CMOS technology show that, compared with the exact multiplier, the lowest-cost design reduces area, power consumption, and power delay product (PDP) by 37.9%, 32.9%, and 83.4%, respectively, while maintaining low NMED and MRED. Furthermore, Gaussian filtering, image sharpening, and Sobel edge detection experiments demonstrate that the proposed accuracy-oriented design maintains high perceptual image quality across different convolution-based image processing tasks.

With the rise of the internet and electronic devices, the security of network information has garnered increasing attention. True Random Number Generators (TRNGs) play an increasingly important role in information security. TRNG entropy sources based on Ring Oscillator (RO) have attracted significant interest due to their simple circuit design and ease of implementation on FPGAs. However, most existing works suffer from high hardware overhead. A novel ultra-lightweight TRNG based on multi-mode switching of RO-like rings is proposed in this work, which can be automatically placed and routed on the Xilinx Artix-7 FPGA, using only 10 LUTs and 2 D flip-flops. The randomness of the entropy source is analyzed through a mathematical model, proving that the output sequence is an unordered random bit string under any circumstances. The output sequence of the TRNG successfully passed various tests, including autocorrelation tests, NIST SP800-22, NIST SP800-90B, AIS-31, and TESTU01, with favorable results.

Optical Proximity Correction (OPC) is a core technology for compensating lithographic diffraction effects in advanced manufacturing processes. Although Inverse Lithography Technology (ILT) enables high-precision mask optimization, it faces challenges in balancing mask printability and optimization efficiency due to three key problems: (1) low-quality initial solutions, (2) high computational overhead, and (3) the inability of pure data-driven methods to accurately model Sub-Resolution Assist Features (SRAF). To address these problems, this paper proposes Hi-ILT, an end-to-end OPC framework that integrates lightweight deep learning and physical ILT correction. A lightweight Convolutional Neural Network (CNN) first generates a high-precision initial mask at low resolution, with a Binary-Straight-Through Estimator (BSTE) resolving binarization gradient vanishing to stabilize training and achieve fast convergence. Subsequently, a gradient descent based ILT correction layer performs fine-grained optimization of mask details (especially SRAF) at high resolution and models process variations. Experiments on 32 nm node M1 layouts (ICCAD 2013 benchmark) and 10 large-scale datasets demonstrate that Hi-ILT outperforms state-of-the-art methods. Compared to deep learning-based ILT methods, it reduces L2 error by up to 30.1%, Process Variation Band (PVB) by up to 19.8%, and Edge Placement Error (EPE) violations by up to 73.4%; compared to gradient descent-based ILT methods, it shortens end-to-end Turn Around Time (TAT) by up to 69.4% while maintaining higher precision. Hi-ILT effectively achieves a balance between high printability and efficient optimization, making it suitable for advanced lithography requirements.

Physical Unclonable Functions (PUFs) leverage manufacturing process variations in integrated circuits to generate unique "fingerprints," which are employed for key generation and identity authentication. However, the challenge-response pairs (CRPs) of PUFs are vulnerable to modeling attacks by machine learning techniques such as logistic regression and neural networks. Current countermeasures include enhancing PUF structures to introduce nonlinearity or employing peripheral circuitry for obfuscation; however, these approaches may compromise reliability or increase hardware overhead. To address this, this paper proposes a machine learning-resistant obfuscated refreshable key PUF architecture, which dynamically obfuscates keys using a lowhardware-overhead, output-uniformity-optimized variant of the PRESENT algorithm. Experimental results demonstrate that the CRPs generated by the proposed PUF architecture on a Xilinx Artix-7 development board achieve machine learning resistance approaching the ideal 50% success rate. Notably, building upon the proposed PUF architecture, this paper further introduces a high-security reconfigurable authentication protocol based on challenge-response partitioning.

A True Random Number Generator (TRNG) is a critical security component that generates unpredictable random numbers based on physical entropy sources, widely used in cryptography, secure communications, and simulation. TRNGs leverage non-deterministic physical phenomena like circuit noise and jitter to ensure randomness. To enhance the security of traditional ring oscillator (RO), multi-phase quantization sampling, logical circuit mapping is realized by using Time-to-Digital Converter (TDC) to improve the performance and security of the entropy source. To meet the demands of high performance and low overhead, this brief proposes a phase-walk based TRNG. By comparing two pairs of ROs and utilizing random phase jitter, the proposed TRNG achieves 600 Mbps throughput on Artix-7, demonstrating unique advantages in resource efficiency and performance.

Strong Physical Unclonable Functions (PUFs) are vulnerable to modeling attacks using Machine Learning (ML), and PUF-based authentication protocols also face security risks. To address these issues, this paper proposes a PUF structure with resistance to modeling attacks based on Dynamic Obfuscation (DO), composed of Linear Feedback Shift Registers (LFSRs), PUFs, and several logic gates. The characteristics of DO are as follows: (1) the initial state of the LFSR is determined by the PUF's response, making it uncontrollable; (2) the updated state of the LFSR determines the obfuscated bit of each input challenge, achieving a dynamic mapping between challenges and responses. An Arbiter PUF (APUF) based on DO is implemented on Xilinx Artix-7 FPGA, and experimental results show that the structure can effectively resist modeling attacks from various ML algorithms, with prediction accuracy close to 50 %. In addition, this paper proposes a mutual authentication protocol based on PUF, suitable for Internet of Things (IoT) systems.

Physical Unclonable Function (PUF), a new hardware security primitive, provides a unique trustworthy root for a system by extracting deviations from a circuit's process. However, existing PUFs are difficult to achieve high reliability under temperature and voltage variations. In this paper, To address the problem of low reliability of Transient Effect Ring Oscillator (TERO) PUF, we propose a feedback TERO PUF based on Mueller gate, which uses the accumulation of RO loop delays to isolate the final PUF response, and stabilises the PUF quickly by introducing the delay of the feedback loop as a threshold. Experimental results on HSPICE show that the FT PUF reduces the BER to the worst 10.28 % over the temperature range of -20-80 degrees C and the voltage range of 0.8-1.2 V, and the uniqueness and uniformity are 51.38 % and 49.87 %, respectively. When implemented on several 7series Xilinx devices, it achieved an 8.07 % reduction in unstable bit rate over conventional TERO PUFs under standard conditions (25 degrees C, 1.0V) and a worst-case unstable bit rate improvement of 3.15 % over the manufacturer's recommended voltage range.

With the rapid development of the Internet of Things (IoT), security issues in resource-constrained devices have become increasingly critical. Physical Unclonable Function (PUF) exploits unavoidable process variations introduced during IC manufacturing to generate unique responses and has been widely used for device authentication and cryptographic key generation. Among various PUF architectures, the Arbiter PUF (APUF) can generate a large number of challenge-response pairs (CRPs) with low hardware overhead. However, its reliability is highly sensitive to environmental variations and device aging, which may degrade the security of authentication protocols. In this paper, a challenge-response remapping reliability enhancement method for APUF based on adjacent challenge-bit flipping is proposed. First, a machine learning (ML) algorithm is employed to construct a software model of the APUF. A delay difference threshold is then introduced to identify challenges whose accumulated propagation delay differences fall below the threshold. Subsequently, specific adjacent bits in these challenges are flipped to transform them into highly reliable challenges. The proposed method is evaluated through Python-based simulations and FPGA-based hardware measurements. Experimental results show that the simulated reliability of the APUF can be improved to 100% under three environmental noise conditions. Moreover, within a temperature range from −20°C to 80°C, the measured reliability of the APUF can also reach 100% without reducing the number of available CRPs. Therefore, the proposed method significantly improves the reliability of APUFs without introducing additional hardware overhead or reducing the number of available CRPs, providing an effective solution for high-reliability authentication in IoT devices.

True random number generator (TRNG) is a key component in ensuring hardware security, and with the development of technologies such as high-speed communications, there is a higher demand for its generation rate. In this work, an ultra-high throughput rate TRNG based on a scalable cascaded full feedback ring oscillator (CFFRO) as the entropy source circuit is presented and implemented on Xilinx Artix-7, Kintex-7 and zynq UltraScale+ FPGAs devices. Unlike previous works, the proposed CFFRO is designed to be constructed as multiple parallel internal ROs, which in turn are sequentially cascaded and coupled to each other to disrupt the frequency spectrum of each ring oscillator and enhance the output uncertainty. Each internal ring oscillator in CFFRO can be used as an output for random numbers, creating multichannel TRNG with parallel outputs and single-channel TRNG with multi-bit serial outputs. Measurements of the sequences extracted by both random number output schemes of TRNG show good randomness in the NIST SP800-22 suits and high entropy values in both the NIST SP 800-90B and AIS-31 testing suits, and the Dieharder suite verified the robustness under voltage and temperature variations. Moreover, due to the good extensibility of CFFRO, TRNGs with 2-8 channel counts are implemented in this work. At a sampling frequency of 400MHz, the random sequences generated by 2-8 channel TRNGs can pass the tests.

The immaturity of manufacturing processes often leads to a high incidence of defects in through-silicon vias (TSVs). Prebond TSV testing is essential for optimizing the yield of chip-based integrated circuits. However, current testing methods are limited by their incomprehensive fault coverage and difficulty detecting subtle defects. Furthermore, these methods exhibit significant performance variability due to changes in process angle, power supply voltage, and temperature (PVT). To overcome these limitations, this article introduces an innovative ring oscillator (RO)-based prebond test method specifically designed for TSVs, with a robust system for defect classification and grading. By sampling each node of the RO oscillating ring, the proposed method enhances the resolution of the Time-to-Digital Converter, thereby improving the defect detection capability. Additionally, a weak current source, constructed utilizing the unique properties of MOS transistors, enables the precise detection of open faults, resistive open defects with R-open >= 1.5 similar to K Omega and leakage defects with R-leak <= 10 G Omega. To further mitigate the impact of PVT variations on test results, this article integrates advanced machine learning techniques for defect classification and grading, providing valuable insights for fault bin classification and fault diagnosis. This innovative approach contributes significantly to the advancement of 3-D IC reliability assessment.

Accurate detection of a wide range of defect patterns on wafers is crucial for enhancing chip yield and ensuring the reliability of semiconductor manufacturing systems. As this process becomes increasingly complex, new types of defects — referred to as unknown defects — emerge on wafers. Traditional pattern recognition methods struggle in this setting because limited samples are insufficient to effectively train deep learning models. Moreover, these models are prone to catastrophic forgetting when incrementally trained on new defect classes. To address these challenges, this paper proposes a method termed Few-Shot Class Contrastive Incremental Learning (FCCIL) for unknown wafer map defect detection. FCCIL integrates a contrastive learning network for distinguishing novel defect types and an incremental learning model for dynamic knowledge updating—both designed to mitigate catastrophic forgetting, thereby enabling the detection of unknown defects in wafer maps with limited data. Experimental results demonstrate a 4% improvement in forgetting resistance over state-of-the-art approaches, confirming the effectiveness of FCCIL in real-world semiconductor manufacturing scenarios.

Arbiter physical unclonable function (APUF) is a hardware security primitive that generates security keys by utilizing unavoidable process variations during chip manufacturing. However, the structure based on linear additive function makes it vulnerable to machine learning (ML) attacks. This paper proposes a parallel feedback obfuscation PUF (PFO PUF) design, which uses intermediate arbitration signals of the lower-layer APUF to generate the hidden challenge of the upper-layer APUF, enhancing the overall nonlinearity of the structure. The obfuscation module makes weight judgment for intermediate arbitration signals of upper-layer and lower-layer APUFs, which obfuscates the real response of PUF. We further design a variant of PFO PUF called reconfigured challenge obfuscation PFO PUF (RPFO PUF) and propose its lightweight device authentication protocol. RPFO PUF enhances the resistance of the original PFO PUF against reverse engineering (RE) and improves its Strict Avalanche Criterion (SAC) characteristic by reordering the challenges and incorporating weak PUF responses. The proposed PFO PUF and RPFO PUF were comprehensively evaluated via Python-based simulations and FPGA measurements. In Python simulations, both designs show strong resistance to state-of-the-art ML attacks, with logistic regression (LR), support vector machine (SVM), and covariance matrix adaptation evolution strategies (CMA-ES) yielding near 50% prediction accuracies under various PUF configurations. Although deep neural network (DNN) achieves up to 69.52% prediction accuracy on the PFO PUF, it drops to similar to 50% on the RPFO PUF. FPGA results further confirm this, with the (32, 11)-RPFO PUF achieving a maximum prediction accuracy of only 51.47% across all four ML attacks. Moreover, both designs incur low hardware overheads, requiring just 743 and 2145 gate equivalents (GEs), respectively.

True Random Number Generator (TRNG) is a critical security component that generates un-predictable random numbers based on physical entropy sources, widely used in cryptography, secure communications, and simulation. This paper proposes a TRNG based on phase delay comparison, where the phase is converted into a control signal via Time-to-Digital Converter (TDC) to implement random delay for the oscillation source. Implemented on an Artix-7 FPGA, it achieves a high 655 Mbps throughput with superior resource efficiency, enhancing security via multi-phase sampling and TDC technology.

Wafer defect classification is a crucial component of semiconductor manufacturing, directly impacting final product quality and yield. Traditional supervised learning methods, which rely heavily on large-scale annotated datasets, often struggle in few-shot scenarios, particularly when encountering previously unseen defect types. To overcome these limitations, we propose a novel few-shot learning framework that integrates dynamic meta-learning with an attention-enhanced prototype network. This framework addresses key challenges such as data scarcity, limited generalization, and the tendency to overfit in low-sample regimes. Specifically, we introduce a dynamic meta-training strategy that adaptively selects task samples to improve cross-task generalization. Furthermore, we design an attention-based prototype network incorporating learnable attention weights to emphasize defect-relevant features, thereby enhancing class discriminability. We integrate task-specific regularization techniques tailored to few-shot learning settings to further reduce overfitting. Experimental evaluations conducted on the MixedWM38 dataset show that our method achieves 82

Background: With the continuous scaling down of integrated circuit feature sizes, the mismatch between the resolution of lithography systems and the feature dimensions leads to undesired shape distortions in wafer imaging, which can cause circuit malfunctions. These distorted regions are referred to as lithography hotspots (LHSs). Therefore, hotspot detection is crucial for ensuring the manufacturability and yield of integrated circuits. Aim: We aim to develop a high-performance hotspot detection framework that enhances feature representation, reduces false alarms, and accelerates inference. It addresses the limitations of existing methods in detecting complex and fine-grained hotspot patterns under advanced process nodes. Approach: We propose a re-parameterizable deep layer aggregation network that employs deep layer aggregation (DLA) to iteratively and hierarchically fuse multi-level features for improved hotspot recognition. The backbone integrates re-parameterizable convolutional blocks to speed up inference, whereas a multi-scale triple fusion (MSTF) module is introduced to further strengthen multi-scale feature integration. Results: We evaluated our method on standard LHS benchmarks. It outperforms state-of-the-art models in accuracy, false alarm reduction, and F1 score while cutting end-to-end runtime. Compared with prior approaches, our method shows measurable gains across all key metrics. Specifically, it delivers notable improvements in both detection performance and efficiency. Conclusions: The proposed DLA-based re-parameterizable architecture offers an effective and efficient approach for detecting LHSs, improving both accuracy and computational efficiency. We point to a practical direction for design that considers manufacturability and could be extended to future studies on hotspot prediction in emerging technology nodes and more complex patterning processes.