This paper investigates the impact of advanced 3D heterogeneous integration on the electrical performance of a $6 \times 50 \mu \mathrm{m}$ GaN-on-Si RF HEMT through detailed characterization. A comprehensive characterization of both DC and RF performance is conducted, focusing on the drain current $(I_{d})$ and the $S_{21}$ parameter, respectively. Additionally, the intrinsic parameters extracted using the small-signal equivalent model of the transistor are analyzed, with particular attention to the measured intrinsic transconductance $\left(\boldsymbol{g}_{\boldsymbol{m}}\right)$. This parameter is further correlated with the device maximum temperature in 3D integration $(T_{\text{max }})$, obtained through thermal simulations. Results demonstrate that the addition of the underfill material alone significantly reduces the temperature and thus improves electrical performance, with the heatsink providing only a minor improvement to the overall balance, whether in terms of thermal or electrical performance.

De-embedding structures (transmission lines, open, short) are costly, whether in terms of silicon area or measurement time. In addition, they lead to measurement inaccuracies increasing with frequency in the millimeter-wave bands. In this paper, we show the possibility to perform de-embedding of HEMT transistors measurements through EM simulations in order to extract the unity-gain cut-off frequency (f(T)). Only an open must be measured to calibrate the EM simulation. Several deembedding techniques are studied and compared up to 67 GHz, based on measurements or EM simulations. The agreement for the extraction of f(T) between measured or EM-simulated deembedding structures validates the proposed approach.

This contribution reports a successfull stacking of an AlGaN/GaN/Si high electron mobility transistor (HEMT) on co-planar-waveguide (CPW) lines fabricated on 200mm Si Trap-Rich substrate. HEMT and CPWs are interconnected with copper pillars (CuPi) using a high-yield chiplet heterogeneous integration process. Thanks to (1) the integration of low insertion loss CuPi interconnects - 0.1dB@28GHz and (2) a careful management of the heat dissipation within the 3D structure, the HEMT transistor features an output power density of 2.2W/mm @10V & a peak PAE of 41%. These RF performances are competitive to other 3D solutions found in the literature. Our industrial grade 3D assembly approach is highly promising for fabricating efficient and cost-effective 3D-RF III-V systems.

The performance of a CMOS-compatible SiN/AlN/GaN MIS-HEMT on 200mm Silicon substrate with high power capabilities in Ka band is evaluated. The devices show an F-t/F-max of 80/170 GHz for 2x50x0.15 mu m(2) topology, along with outstanding and competitive large signal performance compared to GaN/SiC at 40 GHz. The devices demonstrate a power added efficiency PAE of 40% and an output saturated power (Psat) of 6.6 W/mm. To fully benefit from the capabilities of this new technology, an empirical Angelov model was modified to accurately describe the electrical behavior of the devices. The proposed model is validated through 40 GHz load pull measurement/simulation comparison and will be used in designing next MMIC PA (Power Amplifiers) dedicated to Ka-Ku band applications.

We present a study on GaN-on-Silicon high-electron-mobility transistors (HEMTs) designed for high-power RF switch applications. The HEMT are fabricated a fully CMOS-compatible 200 mm process and feature a 100 nm channel length, a recessed gate and an AlN spacer for enhanced performance. Different source/drain widths and spacing are investigated to assess RonCoff vs power handling and linearity trade-offs. The most robust layout achieves a Pmax that exceeds the measurement setup ceiling of 37 dBm. The aggressive layout attains a RonCoff of less than 200 fs and can handle 36 dBm in shunt configuration without requiring device stacking.

We report on the development of CMOS compatible SiN/AlN/GaN MIS-HEMT process on 200mm Si substrates for Ka-band power amplification. The combination of soft gate process, gate design with reduced electric field, in- situ SiN gate dielectric, low temperature ohmic contacts, low substrate RF losses and GaN:C back-barrier leads to Ft/F MAX of 81/173GHz for 2x50μm devices with L G =150nm. At 28 GHz, the device shows performance similar to other GaN/Si technologies at V DD =10V and competitive performance with GaN/SiC at V DD =20V with PAE=41% and P SAT = 6.6W/mm.

A detailed electrical characterization and transistor parameter extraction on 200 mm CMOS compatible GaN/Si HEMTs was performed down to deep cryogenic temperatures. The main transistor parameters (threshold voltage V-th, low-field mobility mu(0), subthreshold swing SS, source-drain series resistance R-sd) were extracted in linear region using the Y-function and the Lambert-W function methods for gate lengths down to 0.1 mu m. The Y-function method was also employed in saturation region for the extraction of the saturation velocity. The results indicate that these GaN/Si HEMT devices demonstrate a very good functionality down to very low temperature with improvement of mobility and subthreshold slope. It was also shown by TLM analysis that the source-drain series resistance R-sd is more limited by the contact resistance than by the 2DEG access region resistance as temperature is lowered.

We present an access technology suitable for scaled gallium nitride (GaN) high electron mobility transistor (HEMT) in Ka-band. The comparison between OFF-state characteristics of a silicon implant-assisted contact and a conventional recessed Ti/Al-based Ohmic contact is presented. The transistor with source/drain extension by Si implantation has a low contact resistance with ${R}_{C}$ down to $0.4 ~\Omega \cdot {\mathrm {mm}}$ and a sheet resistance of the implanted layer of $67~ \Omega $ /sq. In addition to promising contact performance, transistors with source and drain extension sustain high breakdown voltage (BV) with short dimensions for high-frequency applications. The systematic study of gate–source, gate–drain, and gate length variations shows a new breakdown mechanism for implanted access technology with current flowing beneath the channel leading to an unusual correlation between source–drain spacing and BV. With a conventional titanium-alloyed contact, a punchthrough effect is responsible for the BV. Cross-sectional transmission electron microscopy and secondary ion mass spectroscopy (SIMS) characterizations on both wafers highlight a degradation of the AlGaN-based back-barrier and a high silicon concentration deep into the epitaxial stack on the implanted wafers indicating a way to improve BV with an adapted process flow.

In this study, deep traps in multiple-finger normally-off AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) were identified. The localization of these traps has been established by a comparative study using capacitance and current deep level transient spectroscopies (DLTS). The C gd -DLTS measurements cover the GaN buffer region between the gate and drain contacts. On the other hand, the I DS -DLTS measurements cover the channel region in GaN including the zone under the gate. Two electron traps, E2 (0.31eV) and E4 (0.5eV) have been detected. They are respectively attributed to reactive ion etching (RIE) induced surface damage. These two traps are more likely located in the GaN channel close to the gate. Two other deep electron traps E5 (0.64eV) and E6 (0.79eV) have also been detected and are localized in the GaN buffer layer.

A comparative study was performed to assess the gate length effect on trapping properties in AlGaN/GaN metal-oxide-semiconductor channel high-electron-mobility transistors. Deep level transient spectroscopy and electrical simulations were used to investigate the deep levels response in two devices with the same gate surface area but with gate lengths of 15 and 1 mu m. Results reveal that the repartition of equipotential lines depends on the gate length and impacts trapping phenomena. We demonstrated that the concentration of the defects localized beneath the gate electrode and associated with etching induced damage is reduced with a short gate length. Furthermore, for a negative gate voltage, the depletion region is less extended toward the buffer layers with a gate length of 1 mu m, meaning that the trapping effects are reduced. Finally, this work indicates that it is better to design transistors with a short gate length to moderate the effect of trapping phenomena.

The localization of deep traps in normally-off AIGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the equipotential line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a trap with an Ec- 0.5 eV to ion etching induced damage.

Atom chips [1] are an efficient tool for trapping, cooling and manipulating cold atoms, which could open the way to a new generation of compact atomic sensors addressing space applications. This is in particular due to the fact that they can achieve strong magnetic field gradients near the chip surface, hence strong atomic confinement at moderate electrical power. However, this advantage usually comes at the price of reducing the optical access to the atoms, which are confined very close to the chip surface. We will report at the conference experimental investigations showing how these limits could be pushed farther by using an atom chip made of a gold microcircuit deposited on a single-crystal Silicon Carbide (SiC) substrate [2]. With a band gap energy value of about 3.2 eV at room temperature, the latter material is transparent at 780nm, potentially restoring quasi full optical access to the atoms. Moreover, it combines a very high electrical resistivity with a very high thermal conductivity, making it a good candidate for supporting wires with large currents without the need of any additional electrical insulation layer [3].

The semiconductor industry has a highly developed infrastructure for silicon processing with a high level of automation, state of the art facilities and the ability to deal with large volumes which lead to lower fabrication costs. GaN on silicon can take advantage of this maturity of process, especially with the use of 200 mm substrates giving access to large CMOS compatible fabs. This requires specific growth tools with excellent uniformity and low defectivity to ensure compatibility with these processing lines. Combining the industrialization techniques of silicon with the outstanding properties of a wideband gap material such as GaN results in high performance devices and new functionality for a wide variety of applications in power conversion, radio-frequency electronics and opto-electronics. All three of these applications are becoming increasingly present in the global semiconductor market.

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

GaN material holds an advantageous position in the fabrication of power devices. This advantage is manifested by the possibility to perform GaN based devices working in high voltage, high current, high frequency and high temperature conditions. However, despite these theoretical forecasts, trapping mechanisms limit the performances of the GaN based devices revealed by the so-called "drain current collapse". Our study is based on a methodology to understand trapping mechanisms in GaN metal-insulator-semiconductor high-electron mobility transistors. This work was achieved by means of electrical and optical characterization techniques such as Fourier transform deep level transient spectroscopy and photoluminescence. The activation energy and the apparent capture cross section of eight traps were extracted in normally-off (Ids=0A when Vgs=0V) AlGaN/GaN heterostructure technology used for power conversion. Six of these traps, E1=0.16eV, E2=0.31eV, E3=0.46eV, E4=0.5eV, E5=0.64eV and E6=0.79eV are electron traps located in the channel. An identification has been proposed for each trap. Two hole-like traps, H1=0.17eV and H2=0.74eV were assigned to the Mg and C doping of the GaN buffer layers, respectively. These traps might play a role in the current collapse which appears after the application of a large reverse voltage on the gate of the device. Furthermore, the results obtained using electrical and optical techniques allowed concluding that oxygen atoms and dislocations are incorporated in GaN layers during the growth.

For the first time, ultrafast AC pBTI measurements are applied to GaN on Si E-mode MOSc-HEMT and compared to DC pBTI. Full recess Al2O3/GaN MOS gate is submitted to AC signals with various frequencies, duty factors and stress times. The degradation and relaxation characteristics are then modeled through a RC model combined to a CET map and fitted to experimental data. This map reveals the presence of two trap populations, also observed through ΔVth degradation kinetics. Acceleration factors (gate voltage and temperature) are estimated as well as TTF (Time to Failure) under AC conditions and show an extended lifetime compared to DC stress conditions. Finally dynamic variability is studied and indicates that our devices are ruled by normal distributions.

GaN on silicon is an extremely promising substrate for the production of high-performance power devices, with the potential for reducing losses and operating at higher frequencies and temperatures while keeping costs low. This chapter analyzes the challenges for this technology, from the substrate strain and current leakage management to the device performance in static- and high-frequency operation, with a final focus on thermal management. We look at how the understanding of these problems has developed and how the challenges are being overcome, as GaN on silicon becomes viable for the production of high-power transistors on 150 and even 200 mm wafers, using CMOS-compatible production tools.

Power diodes or transistors must be able to work in high voltage/high current use, for instance in AC/DC converters. However, in such aggressive conditions trapping effects can occur. In this work, a negative voltage stress has been applied to AlGaN/GaN Schottky barrier diodes by sweeping the bias from 0 V to − 600 V. This voltage corresponds to the real conditions of use of the power diodes. Using deep level transient spectroscopy measurements, we demonstrated that five traps labeled E1, E2, E3, B and A with activation energies 0.4, 0.44, 0.50, 0.58 and 0.65 eV respectively, are linked to the effects of the negative bias stress. Trap E2 has been localized in the channel region and carbon impurity is expected to be involved in trap E1. We demonstrated that no significant contribution on the reduction of the sheet carrier concentration in the channel can be attributed to these deep traps.

pGaN Gate HEMTs are promising normally-OFF transistors for which the use of magnesium (Mg) doping allows the modulation of the threshold voltage (Vth) but at the cost of an ON-state resistance (Ron) degradation. In this study, we propose rigorous TCAD simulations that describe the Mg doping impact on both electrical parameters (Vth and Ron) in agreement with experimental data. We emphasize the importance of TCAD as an additional tool to optimize this Vth-Ron process-window.

A novel GaN on Si device is presented and tested in an “application like” circuit. The device is a Bi-Directional Normally-Off Switch aimed at AC mains powered applications, it uses a single reference electrode for gating direct and reverse conduction modes. Demonstration of the current collapse free operation of the device under 264V, 3A, 1MHz is presented.