Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.

Large-scale cryogenic quantum systems are constrained by an input-output bottleneck between room-temperature electronics and millikelvin stages, particularly in superconducting qubit platforms. This bottleneck is most acute for output lines, where bulky and expensive microwave components limit scalability. A promising approach for scalable characterization and testing is to perform signal multiplexing directly at the qubit plane. We demonstrate a cryogenic CMOS (cryoCMOS) RF multiplexer operating at 10 millikelvin with record-low static power consumption of 200 pW. The device provides < 2 dB insertion loss and > 30 dB isolation across DC-8 GHz. Direct connection to transmon qubits marginally affects coherence times in the range of 100 microseconds, enabling multiplexing of readout, flux and, in principle, XY drive lines. This work introduces cryoCMOS multiplexers as valuable tools for scalable, high-throughput cryogenic characterization and testing, and advances co-integrated quantum-classical control for future large-scale quantum processors.

High 1/f noise in CryoCMOS devices is a critical parameter to keep under control in the design of complex circuits for low temperatures applications. Current models predict the 1/f noise to scale linearly with temperature, and gate oxide defects are expected to freeze out at cryogenic temperatures. Nevertheless, it has been repeatedly observed that 1/f noise deviates from the predicted behaviour and that gate oxide defects are still active around 4.2 K, producing random telegraph noise. In this paper, we probe single gate oxide defects in 2500 nMOS devices down to 5 K in order to investigate the origin of 1/f noise in CryoCMOS devices. From our results, it is clear that the number of defects active at cryogenic temperatures resulting in random telegraph noise is larger than at 300 K. Threshold voltage shifts due to charged defects are shown to be exponentially distributed, with different modalities across temperatures and biases: from monomodal at 300 K to trimodal below 100 K. The third mode is interpreted in the framework of percolation theory. By fitting these distributions, it is shown that more than 80

The increasing interest in cryogenic circuits is driven by their transformative potential across high-performance computing, medical devices, space exploration, and quantum technologies. Operating transistors at cryogenic temperatures, such as 77 K and below, yields substantial improvements, including increased ON current, reduced OFF current, and enhanced sub-threshold slope, paving the way for significant gains in efficiency. While recent studies have explored device-level reliability at cryogenic temperatures, circuit-level reliability-particularly under bias temperature instability (BTI) and hot carrier degradation (HCD)-remains underexamined, leaving critical aging mechanisms at these temperatures poorly understood. To bridge this gap, we designed and fabricated a fully customized chip in a commercial 28 nm technology. The chip integrates diverse ring oscillator (RO) circuits for precise characterization of BTI and HCD aging effects, enabling evaluation of their impact on performance at cryogenic temperatures as low as 4 K. This work ensures that as cryogenic CMOS technologies drive innovation in critical applications, their reliability is comprehensively understood and advanced.

Testing of spin-based quantum devices is currently performed through quantum dot and qubit measurements at deep cryogenic temperatures, well below 1 K. At such low temperatures, the testing throughput is strongly limited due to the long cool-down times and due to the large number of connections required between the device at deep-cryogenic temperature and the room-temperature control electronics. As the number of qubits in a single chip increases and as we advance toward large-scale manufacturing, developing effective techniques that allow to screen those chips at higher temperatures, possibly even room temperature, becomes indispensable. Transistor metrics constitute a promising indicator to identify, at room temperature, which devices are functional and also at cryogenic temperatures. Prior work has demonstrated a strong correlation between quantum dot metrics measured at deep-cryogenic temperature and transistor metrics up to 77 K. To ensure that such a correlation extends up to room temperature, electrostatic confinement of the conductive channel needs to be guaranteed. In this article, we propose a single-electron transistor (SET) design intended for the correlation study of transistor metrics from deep-cryogenic up to room temperatures. Our calibrated technology computer-aided design (TCAD) simulation results demonstrate the drastic improvement of the room-temperature transistor behavior of the proposed design, without the employment of physical device isolation that would negatively impact the qubit’s fidelity. In addition, this work presents a room-temperature-aware methodology in the design phase of spin-based devices, with promising scalability to structures containing a larger number of qubits.

We extend our compact physics model (CPM) for hot-carrier degradation (HCD) to cover the impact of ambient temperature on HCD. Three components of this impact are taken into account. First, variations in temperature perturb carrier transport. Second, the thermal component of Si-H bond rupture becomes more prominent at elevated temperatures. Third, vibrational lifetime of the bond decreases with temperature. While the first and the third mechanisms impede HCD, the second one accelerates this detrimental phenomenon. The aforementioned mechanisms are consolidated in our extended CPM, which was verified against experimental data acquired from foundry quality n-channel transistors with a gate length of 28 nm. For model validation, we use experimental data recorded using four combinations of gate and drain voltages and across a broad temperature range of 150–300 K. We demonstrate that the extended CPM is capable of reproducing measured degradation ΔId,lin(t) (normalized change of the linear drain current with stress time) traces with good accuracy over a broad temperature range.

Electron-spin qubits are among the most promising platforms for the realization of a large-scale quantum computer. Physical limitations dictate their operation at cryogenic temperatures, in practice often well below 1 K. This requirement implies the employment of a refrigerator featuring long cooldown times and the need for die packaging, thereby strongly limiting the number of devices that can be measured simultaneously. In our work, we evaluate traditional transistor metrics to enable fast wafer-level screening of electron-spin qubit devices above cryogenic temperatures. To the best of our knowledge, a clear link between quantum dot metrics measured below 2 K and traditional transistor metrics measured at higher temperatures has not yet been identified. In this paper, we study the correlation between 10 mK measurements in the few-electron regime, and traditional transistor metrics at different temperatures. We observe a strong correlation up to 77 K, while correlations at higher temperatures are much less pronounced. We analyze this poor correlation via room-temperature TCAD simulations, showing that the underlying physics changes due to a considerable contribution of the substrate current to the device’s off current above 77 K.

The performance of nanosheets with a gate length of 14 nm is investigated by Monte Carlo (MC) and drift–diffusion (DD) simulation between 77 K and 400 K. Increasing at fixed workfunction the temperature from 300 K to 400 K leads for MC to an on–current (ION) increase as opposed to a reduction in DD. This is related to the quasi–ballistic regime which involves little phonon scattering reducing the temperature–induced penalty in contrast to a strong phonon–limited mobility degradation in DD. The same physics yields below 300 K to a stronger ION improvement for DD than for MC. In addition, the subthreshold swing is below 300 K for MC substantially worse than for DD. These results will have a strong impact on the thermal limitations of chip operation and the viability of cold CMOS.

In this work, impact of cryogenic operation temperatures on latchup in 28nm planar bulk CMOS technology is discussed for quantum computing applications. Measurement and simulation results indicate that at low temperatures the sheet well resistances experiences 60% increase. Further simulations reveal that the vertical resistance increases leading to latchup risk. However, the current gain product of the parasitic bipolar transistors reduces, and holing voltage is increased with low temperatures which can compensate the latchup risk.

Net benefits of cold CMOS including the refrigeration penalty are investigated for datacenters. It is found that cold CMOS is best used in the iso-speed (energy efficiency) scenario at moderately low temperatures above -50 degrees C. Total energy reduction at iso-speed is -30% with LCO2 (-50 degrees C) and -10% with LN2 (77 K, -196 degrees C) for 40% of Carnot cooling efficiency. The optimal die temperature is around -20 degrees C. Highspeed scenario (same compute power) is less interesting because total energy increases more rapidly than delay reduces (2 X for -20% at -50 degrees C) and heat transfer is limited for LN2 (<30 W/cm(2)). Overall, LCO2 CMOS at iso-speed (V-DD approximate to 0.6 V) can improve datacenter sustainability in terms of energy efficiency, power density, and environmental impact. Power density in emerging 3D stacked CMOS architectures can be reduced even if total-energy savings shrink to -0%. LCO2 is a welcome replacement for the fluorinated coolants being phased-out due to their high global warming potential of 25.000 CO2-equivalent, and LCO2 batteries can store the fluctuating green energy while preserving rare-earth metal deposits and promoting geopolitical independence. To obtain more than -30% theoretical total energy reduction with voltage-scaled classical CMOS, further advances are required in cooling efficiency (>40%) and/or (transistor) compute-power reduction (V-DD < 0.6 V). Further V-DD-scaling at iso-speed is hampered by the requirement to beat Boltzmann's thermal limit. This could open up a new field of research on super-steep-slope devices achieving sub-thermionic behavior at moderately low temperatures instead of at room temperature.

The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative average performance of the devices and provided a large effective area for 1/f noise analysis. Results showed an improvement in the saturation drain current when going from room temperature to cryogenic temperatures, with the subthreshold swing saturating around 100 K and the threshold voltage shifting by approximately 150 mV, following similar trends observed in Silicon cryogenic electronics. Additionally, the study confirms that the noise at cryogenic temperatures does not follow the commonly assumed linear scaling with temperature. This deviation from the linear scaling has been associated with the presence of tail states at the interface in bulk and silicon-on-insulator (SOI) devices. These results suggest that the excess 1/f noise in this advanced device architecture is not related to the device architecture but rather to the microscopic material properties of semiconductor/dielectric interfaces.

We present a full electrical characterization of a commercial 16 nm FinFet technology conducted at six different temperatures, from 300 K to 4.2 K. First, we explore the electrical performance, with particular emphasis on the unconventional oscillatory behavior observed in strong inversion at temperatures below 50 K. This is usually attributed to the 1D subbands filling by the inversion carriers. We then introduce a Lambert-W function-based model to extract the devices’ main figures of merit, and its effectiveness is demonstrated down to liquid helium temperature. Finally, we investigate device to device variability. Although the impact of the above-mentioned oscillations worsens the local variability at cryogenic temperature, 16 nm FinFet technology electrical and mismatch performance surpasses the planar technology ones.

Any product that stops functioning before its declared useful lifetime will be deemed substandard at best, dangerous or fatal at worst. Integrated circuits (ICs) are typically a part of a larger product, which, depending on the target market, may be expected to operate reliably for up to multiple decades, often in extreme environments, and in mission-critical applications. It is therefore essential that reliability is engineered into the ICs and their individual components already during their development, and not ignored altogether, or merely evaluated as an afterthought.

Quantum dot (QD) formation in multiple-gate FETs is a promising solution to scale QD-based devices. In this work, we report on the superiority of the quantum mode performance of SOI-gate-all-around nanowire FETs (GAA NWFETs) compared to the bulk FinFETs. A classical comparison is followed by an investigation based on the quantum perspective. The Coulomb blockade region is analyzed through the drain current oscillations at cryogenic temperatures. Performance metrics of the FET channel QDs are compared. NWFETs show better quantum confinement properties at much relaxed geometries than the bulk FinFETs, which makes them a potential candidate for scalable integration of QD-based qubits for the quantum processing units (QPUs). To assist in the design of QD-based charge/spin qubits, a subcircuit-based proximity charge sensing model is proposed. The model augments the existing BSIM CMG-based compact model to capture the charge sensing characteristics of a single-electron transistor (SET). This, in turn, can aid the layout design for CMOS-based QPUs.

Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.

Large-scale superconducting quantum computing systems entail high-fidelity control and readout of large numbers of qubits at millikelvin temperatures, resulting in a massive input-output bottleneck. Cryo-electronics, based on complementary metal-oxide-semiconductor (CMOS) technology, may offer a scalable and versatile solution to overcome this bottleneck. However, detrimental effects due to cross-coupling between the electronic and thermal noise generated during cryo-electronics operation and the qubits need to be avoided. Here we present an ultra-low power radio-frequency (RF) multiplexing cryo-electronics solution operating below 15 mK that allows for control and interfacing of superconducting qubits with minimal cross-coupling. We benchmark its performance by interfacing it with a superconducting qubit and observe that the qubit’s relaxation times (T1) are unaffected, while the coherence times (T2) are only minimally affected in both static and dynamic operation. Using the multiplexer, single qubit gate fidelities above 99.9%, i.e., well above the threshold for surface-code based quantum error-correction, can be achieved with appropriate thermal filtering. In addition, we demonstrate the capability of time-division-multiplexed qubit control by dynamically windowing calibrated qubit control pulses. Our results show that cryo-CMOS multiplexers could be used to significantly reduce the wiring resources for large-scale qubit device characterization, large-scale quantum processor control and quantum error correction protocols.

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT). In this work we present Comphy v3.0, an open source physical framework for modeling these effects in a unified fashion using nonradiative multiphonon theory on a one-dimensional device geometry. Here we give an overview about the underlying theory, discuss newly introduced features compared to the original Comphy framework and also review recent advances in reliability physics enabled by these new features. The usefulness of Comphy v3.0 for the reliability community is highlighted by several practical examples including automatic extraction of defect distributions, modeling of TAT in high-k capacitors and BTI/RTN modeling at cryogenic temperatures.

We extend our compact physics model for hot-carrier degradation (HCD) by implementing the contribution to damage caused by the secondary carriers (generated by impact ionization) and revisiting transport modeling for primary carriers. To verify the model we employ planar field-effect transistors (FETs) with a gate length of 28 nm, which were subjected to HC stress under $V_{\text{gs}}=V_{\text{ds}}(V_{\text{gs}}$ , and $V_{\text{ds}}$ are gate and drain voltages, respectively) and at conditions with $V_{\text{gs}}$ much lower than $V_{\text{ds}}$ . We show that in the former case the contribution of secondary holes is small, whereas at lower $V_{\text{gs}}$ the secondary holes result in a substantial portion of damage, especially at higher $V_{\mathrm{d}\mathrm{s}}$ . Finally, we show that the model can accurately capture experimental changes of the linear drain current induced by HC stress.

We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages (Vgs and Vds, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low Vgs and relatively high Vds. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages {Vgs,Vds}.