Embedded EEPROM technologies are widely used in industrial microcontrollers and offer excellent reliability, but their potential for analog operation remains under-explored due to the limited observability of cell-level electrical behaviour in standard memory arrays. This work leverages the SuperCAST test structure, a fully addressable 4k-cell EEPROM array, to perform detailed analog characterization of floating-gate devices. The architecture provides individual access to each memory cell, enabling pulse-by-pulse programming analysis, variability extraction, endurance and retention evaluation, and precise readout characterization. These measurements allow assessing the suitability of EEPROM technology for analog synaptic operation in neuromorphic systems. Finally, the experimentally extracted characteristics are incorporated into neural-network simulations to illustrate how device-level non-idealities impact learning performance. The results demonstrate that SuperCAST is a powerful platform for evaluating embedded EEPROM as a candidate for reliable analog in-memory computing.

This study investigates the variability in HCI (Hot Carrier Injection) degradation within a 4 kb charge storage memory array, manufactured on a dedicated wafer split process. A standard set of experiments is conducted to extract electrical features of the cells before and after stress. A statistical analysis method, based on the Principal Component Analysis (PCA) approach, is introduced to enhance the comprehension of the cell degradation prior to reliability testing. Additionally, a graphical model is developed to identify extrinsic cells in the memory array prior to stress, as well as to assess the overall technology yield. Finally, others classifier models are explored aiming to improve extrinsic cells detection before running the reliability test.

Embedded non-volatile memory are still largely used in automotive and IOT products [1], thanks to their robustness and reliability performances. The embedded Select in Trench Memory (eSTM™) is a 40 nm split-gate technology developed by STMicroelectronics [2] that allows high speed and low energy consumption for microcontrollers applications. To deep understand the degradation mechanisms, we developed a Test Structure with Two Active (TSTA) [3] based on eSTM™ architecture. This dissociate write and erase operations for oxide reliability studies. The TSTA used for this experimental study is shown in Fig. 1. One of the main oxide degradations occurs at the interface between the polysilicon floating gate and the trench selector. Previous studies [4] have shown that overlap architecture improves the programming window of eSTM™. In this article, the key role of the floating gate shaped tips is studied by modifying the fabrication process, specifically by adjusting the height of the trench selector polysilicon. Thus, the impact of this process step, on the cell performances, has been experimentally demonstrated. The process follows the usual eSTM™ fabrication steps until the trench definition [5], where process adjustments are made. It is then completed with the memory stack. As shown in Fig. 1 b, the in-trench polysilicon deposition (Poly0) that forms the select transistor is not aligned with the p-substrate surface. This allows the formation of tips at the interface between the bulk, floating gate, and selector (CG-SEL). To study the device behavior using the TSTA, we enhanced the Fowler-Nordheim tunneling in this region, as shown in Fig. 2, by splitting the potential between the trench selector and control gate nodes. For V CG = -8 V and V SEL = -8 V, the TSTA is erased improving the high electrical field at the tip location. However, in these conditions the TSTA is not robust to WordLine (WL) disturb at the memory array level, which can occur during cell reading when the select transistor is at V Sel = 3V. As an alternative, it is thus possible to use the Select and CAPA implant nodes to erase the TSTA. Moreover, on the other active region, the SSI injection degradation can be studied without any parasitic electric field. To improve the robustness of the trench selector fabrication, Chemical and Mechanical Polishing (CMP) is performed after trench oxide growth. Different timings are used to adjust the height of Poly0 compared to the P-well active, presenting recesses for +0 sec, +10 sec, +20 sec, and +50 sec (Fig. 3 a,b,c,d). This provides a trend of the height gain evolution in this specific area. The timing has no impact on the aspect ratio of the Poly0 filling. However, voids in the trench are detected for high recess processes (Fig. 3 d). Afterward, tunnel oxide growth is performed. We observe that for a recess of +20 sec, the substrate and Poly0 are well aligned, which implies a planar growth of tunnel oxide. This ensures a memory stack process fabrication without any tip formation. These morphological results are promising for electrical measurements, which will be carried out on finished wafers. This study highlights the select transistor weaknesses induced by the floating gate tip without any height adjustment. By using usual process steps, these issues are resolved, providing promising advanced electrical characterizations using TSTA as a memory architecture for reliability studies using SSI and FN tunneling. Finally, TCAD simulations have been performed to understand the intrinsic behavior of tunneling through tips for split-gate memory cells. [1] R. Strenz, "Review and Outlook on Embedded NVM Technologies – From Evolution to Revolution," 2020 IEEE International Memory Workshop (IMW) , Dresden, Germany, 2020, pp. 1-4, doi: 10.1109/IMW48823.2020.9108121. [2] F. L. Rosa et al. "40nm embedded Select in Trench Memory (eSTM) Technology Overview," 2019 IEEE 11th International Memory Workshop (IMW) , Monterey, CA, USA, 2019, pp. 1-4, doi: 10.1109/IMW.2019.8739731. [3] K. Alkema et al . "A novel test structure with two active areas for eNVM reliability studies," 2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS) , Edinburgh, United Kingdom, 2024, pp. 1-5, doi: 10.1109/ICMTS59902.2024.10520674. [4] Franck Melul et al. “Morphology and reliability aspects of 40 nm eSTM™ architecture”, Microelectronics Reliability, Volume 126, 2021, 114266, ISSN 0026-2714 [5] S. Niel et al . "Embedded Select in Trench Memory (eSTM), best in class 40nm floating gate-based cell: a process integration challenge," 2018 IEEE International Electron Devices Meeting (IEDM) , San Francisco, USA, 2018, pp. 7.4.1-7.4.4, doi: 10.1109/IEDM.2018.8614517. Figure 1

The integration of PN diodes on bulk silicon technologies often leads to shot noise and significant parasitic effects such as latch-up which arises when a parasitic transistor is unintentionally triggered, leading to undesired current flows. To address these issues, and enable operation in higher voltage ranges, this work investigates the use of unexplored polysilicon PIN diodes implemented on an insulating area as an alternative solution to PN diodes integrated on bulk substrates. The geometric design and process optimizations of the PIN diode structure are explored to optimize its performances (forward and leakage currents, series resistance, threshold, and breakdown voltages) while ensuring compatibility with low-cost analog circuits fabricated in an 40nm technology dedicated to IoT applications. Compared to classical PN diodes, PIN diodes require a simple fabrication process and can provide a breakdown voltage twice higher. However, this improvement comes at the expense of an increased leakage current and series resistance.

Precise measurement of gate and gate-to-drain/source overlap capacitances of MOS transistors is essential during technology development to assess process trial effects on MOS electrical parameters and monitor process variations. Measuring such low-value capacitances is challenging with external equipment due to additional parasitic capacitances. This work presents a fast and accurate oscillator-based embedded capacitance measurement system targeting MOS transistor capacitances. The capacitance values are converted into easily measurable oscillation frequencies using ring oscillators. The system includes multiple selectable ring paths loaded with known-value capacitors for calibration. Once calibrated, it enables the evaluation of unknown capacitances. Simulation results in a 40 nm CMOS technology, including post-layout simulations, confirm the feasibility and accuracy of the proposed approach.

As the demands of RF applications are rising, optimization of internal MOSFETs capacitances is a key issue to improve the cut-off frequency. In this abstract we report the development of a novel N-MOS architecture processed on 8-inch SOI wafers. This architecture has a gate oxide with variable thickness along the channel and a reduced bottom gate length aiming at minimizing Gate to Drain/Source capacitance (1) (2). This improvement on Gate to Drain/Source capacitance mainly comes from a decrease in overlap capacitances as described in (3). The new process flow is composed as usual until Poly-Si gate etching. By controlling the species flow and process time during plasma etching steps, over etch at the bottom of the gate is performed (fig.1(a,b)). Poly-Si gate notching engineering is possible due to reduction of the passivation layer thickness at the bottom of the gate during plasma etch. As described in (4) the gate is first etched using a HBr/CL2/O2 chemistry until reaching close to the bottom of the gate, allowing the formation of a passivation layer made of SiOxCly and the anisotropy of the etch. To etch the remaining thickness HBr flow is augmented while CL2 and O2 flow are reduced, preventing formation of passivation layer. This leads to isotropic etch of the bottom gate and reduction of the gate length as regard to the top Poly-Si dimension. This over-etch reduces the physical gate length without changing the effective and the on-mask gate lengths, leading to overlap capacitance reduction. To produce gate oxide with variable thickness under gate sidewalls a two-steps process is performed. First, full plate oxide is grown before poly-Si deposition to act as middle gate thickness. Then undercut is performed, consisting of lateral etching of the gate oxide under gate sidewall after gate etch (fig.2.a). To achieve this undercut, hydrofluoric acid (HF) wet etch has been chosen. First trials with very low HF concentration become quickly saturated leading to small lengths under gate sidewalls (fig.2.b). Then more acidic solutions were used allowing satisfying undercut lengths (fig.2.c). Finally rapid thermal oxidation (RTO) is performed to obtain an oxide bird beak at both gate side as both Poly-Si gate and Si from the active region react with ambient O2 in the chamber. This leads to a gate oxide with variable thickness along the channel (fig.3(a.b)) which has both effects: to get smoother poly-Si foot and a down step in the active between channel and Source/Drain regions. During this process step, a built-in spacer on the gate sides for LDD implantation is formed. RTO process step has grown a thicker oxide over Source/Drain areas which has to be reduced to allow an accurate LDD implantation, this is done by anisotropic etching. After these new steps, the process goes back to a standard N-MOS process flow. Some early versions of the notched gate have been investigated (5), and these experiments and details on processing recipe seem promising for electrical results. As poly-Si foot has been smoothed and graded gate oxide (GGO) on top of overlaps region is formed. It would allow a reduction in parasitic capacitances improving cut-off frequency of RF applications. References RF LDMOSFET with Graded Gate Structure. Xu Shuming, Foo Pan Dow. Toronto : s.n., 2001. 1th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings. pp. 221-224. DOI:10.1109. Notched-Gate pMOSFET with ALD TiN/High-κ Gate Stack Formed by Selective Wet Etching. Zhang, D. Wu and J. Lu and P.-E. Hellström and M. Östling and S.-L. s.l. : The Electrochemical Society, Inc., 2004, Electrochemical and Solid-State Letters, Vol. 7, p. 228. 10.1149/1.1795612. A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs. Fabien Pregaldiny, Christophe Lallement,Daniel Mathiot. s.l. : Solid State Electronics, 2002, Vol. 46, pp. 2191–2198. https://doi.org/10.1016/S0038-1101(02)00248-4. Design of notched gate processes in high density plasmas. J. Foucher, G. Cunge, L. Vallier, and O. Joubert. s.l. : AVS: Science & Technology of Materials, Interfaces, and Processing, 2002, Vols. Journal of Vacuum Science & Technology B 20,. http://dx.doi.org/10.1116/1.1505959. Notched gate MOSFET for capacitance reduction in RF SOI technology. al, L. Antunes et. s.l. : 2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS), 2023. doi: 10.1109/DTTIS59576.2023.10348288. Figure 1

This paper presents a test structure with a poly floating gate shared on two actives areas. Programming and erase can be split toward these two regions with a specific arsenic implantation. The aim is to study the tunnel oxide degradation and the injection efficiency of embedded charge storage memory cells.

In this paper, we discuss a new development of 40nm SONOS eSTM™ (embedded Select in Trench Memory). We present an experimental study based on hot carrier injection mechanism for both programming/erase operations, performed on this new eNVM architecture. The optimization of drain and select gate biases, in order to define the programming and erasing threshold voltages, is also detailed. All the characterizations have been carried out for two different SONOS eSTM™ architectures giving an opportunity to propose different solutions. One of this using a continuous silicon nitride layer for two neighbour cells, taking advantage on the discrete charge trapping nature. As well, we performed endurance tests up to one million cycles for both architectures to evaluate the memory endurance.

Reduction of parasitic front-end capacitance is one of the key factors to improve the performance of RF applications. In this work, we report the development of an atypical gate architecture allowing the reduction of the source/drain overlap capacitances of a PD-SOI n-MOS transistor. After presenting the process flow and monitoring methods, we discuss the low frequency and RF electrical results such as C OFF , R ON , RF Vmax .

Over the years, RFSOI has emerged as dominant technology for building RF FEM modules with optimum cost and performance. RFSOI switches are typically designed using thick gate oxides with biasing up to 3. 3V to deliver minimum RON x COFF. With the strong push of operating digital devices at lower voltages, it would become necessary to evaluate the performance of the switch under such operating conditions. In this paper, we analyze the impact of RON x COFF of the switch in 200mm RFSOI technology, under scaled bias conditions and propose path for device optimization.

In this work, ring oscillator test structures are designed and characterized to evaluate the in-circuit performance of a new medium-voltage (around 2-5 V) transistor architecture developed via process optimization in a 40 nm embedded non-volatile memory (eNVM) CMOS technology. The transistor is zero-cost in terms of photomask and process steps. It is compared to an existing transistor available in the technology. A SPICE model (Simulation Program with Integrated Circuit Emphasis) of the new device is developed to evaluate its circuit-level performance through electrical simulations. The simulation results are complemented by experimental results, and both show a large increase in the ring oscillator frequency for the new transistor, compared to the existing one. In addition, the reliability of the new transistor is evaluated at the device level with hot-carrier injection (HCI) stress tests and at the circuit level with power-supply stress tests.

Schmitt triggers are useful circuits in analog and digital domains, and they can be used to highlight the strengths and weaknesses of their constituent transistors. In this paper, a benchmark of a new zero-cost (in terms of process steps) medium-voltage transistor build via process optimization is performed in a 40 nm CMOS low-cost technology using Schmitt triggers. The process optimization lowers the threshold voltage, increases the ON-state current at the cost of increasing the OFF-state leakage current and the gate oxide capacitance. A circuit-level study is conducted to see how these characteristics translate into the performance of a Schmitt trigger. Measurements show a good correlation between the transistor-level performance and Schmitt trigger figures of merit.

As with many circuit building blocks, a digital-to-analog converter (DAC) can directly highlight the strengths and weaknesses of its constituent transistors. In this paper, a new zero-cost middle-voltage transistor is proposed by reusing already existing process steps and photomasks in an embedded non-volatile memory CMOS technology. Special attention is given to the matching performance of this new transistor. It is benchmarked against existing transistors of the technology, first at the transistor level, and then at the circuit level using a simple DAC structure. DAC-related measurements such as linearity error are compared to the more traditional method of measuring transistor matching performances. Experimental results show better matching performance for our new zero-cost transistor than the existing high-voltage device available in the technology but not optimized for analog applications. A strong link is observed between the transistor-level matching performance and the DAC linearity.

Electrically Erasable Programmable Read Only Memory (EEPROM) is a widely used memory device, nowadays implemented in submicron technology nodes. In this paper we show how the well-known trapping power law found in the literature can be retrieved by combining well calibrated state of the art Technology Computer Aided-Design (TCAD) simulations with a compact model for tunnel oxide degradation during EEPROM cycling. We pinpoint how this approach can be used to predictively assess the programming window closure and consequently, considerably reduce the time-consuming cycling test procedure. Finally, we show how this methodology can cover a wide range of temperatures, making it very attractive for high demanding applications such as automotive.

In this paper we present a full free addressable 4kb EEPROM memory array. This test structure based on CAST vehicle has been upgraded with flexible addressing logic to select any numbers of cells on single or multiple word lines. To this aim, column/row shift registers, to enable an easy cell biasing, have been implemented in an embedded non-volatile memory environment. High voltage circuits, driven by low voltage shift registers, are used to bias selected cells for electrical characterizations and reliability tests purposes. This kind of structure has been developed to improve the efficiency of electrical characterization laboratory, resulting in an enhanced acquisition with respect to standard CAST test techniques, opening the path to fine statistical analysis.

This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor.

The Electrically Erasable Programmable Read Only Memory (EEPROM) technology has been widely studied but EEPROM Technology Computer Aided-Design (TCAD) simulations still need to be improved to handle the rises of the quality requirements of the semiconductor market. In this paper, the impact of endurance degradation on EEPROM programming window and the corresponding TCAD simulation are investigated. Advanced calibrated TCAD simulation on 110nm node is used to evaluate the distribution of negative charges trapped in the tunnel (bulk) oxide during EEPROM cycling. The total negative charge evolution found by our simulation is in agreement with the well-known trapping power law found in the literature.

In this paper, we present an experimental study of a new architecture of the embedded Select in Trench Memory (eSTMTM) cell. A first part is dedicated to a deep analysis of the overlap eSTMTM behaviour. A key fact is the possibility to achieve a large programming window thanks to tip effect enhanced erase. After the study on erase operation scheme, we demonstrate the impact of Select to Floating gate tip coupling on the endurance results. The endurance results are thus improved up to 500 k cycles using the overlap eSTMTM.

In this paper, we detail an experimental study of the hot electron Source Side Injection programming operation of the embedded Select in Trench Memory (eSTM™) cell. A complete set of electrical characterizations is carried out. A focus on the Select Gate bias to improve the programming window and the consumption is reported. Moreover, the impact of the Sense-to-Select distance, on the memory behavior is highlighted. These characteristics give us the keys to find the best tradeoff to program this cell. Finally, the optimized programming scheme is used to show the endurance up to 500k cycles, while the programming current is monitored. We report an energy consumption decrease during the cycling thanks to the Source Side Injection mechanism. This makes the eSTM™ cell suitable for low-power and scalable embedded applications.