As 6G connectivity demands to improve up-to-date CMOS Silicon-on-Insulator (SOI) RF Front End Modules (FEMs) performances, lower R-ON center dot C-OFF values are required for the next generation of switches, while maintaining equal or higher breakdown voltages. In this paper, we demonstrate that reducing SOI thickness is an effective approach for pushing further the capabilities of modern RF switch devices, diminishing parasitic capacitance COFF without affecting devices power handling. With respect to our technology reference, R-ON center dot C-OFF has been reduced by 14%, achieving R-ON center dot C-OFF/RFVMAX state-of-art values of 74fs/3.3 V. Furthermore, RF breakdown is studied, revealing that the dominant reason that limits power handling in OFF-state conditions is leakage current, ascribed to Gate-Induced Drain Leakage (GIDL), parasitic bipolar triggering, and punch through. In addition, a non-destructive method to estimate RFVMax value by means of DC measurements is proposed, providing a rapid and reliable in-process-line method for power handling characterization of RF switch devices.

In this paper, we discuss a new development of 40nm SONOS eSTM™ (embedded Select in Trench Memory). We present an experimental study based on hot carrier injection mechanism for both programming/erase operations, performed on this new eNVM architecture. The optimization of drain and select gate biases, in order to define the programming and erasing threshold voltages, is also detailed. All the characterizations have been carried out for two different SONOS eSTM™ architectures giving an opportunity to propose different solutions. One of this using a continuous silicon nitride layer for two neighbour cells, taking advantage on the discrete charge trapping nature. As well, we performed endurance tests up to one million cycles for both architectures to evaluate the memory endurance.

We focus on slip line formation and propagation on different types of Si and SOI substrates that underwent high temperature anneals during 65nm RFSOI device fabrication. Different parameters are found to contribute to slip line formation and dislocations propagation, mainly the substrate properties (thickness, layer and oxygen in silicon handle), the temperature gradients and the support between furnace carriers and backsides of substrates. Several parameters contribute to substrate deformation, e.g. the warpage increase. The warp degradation is found to be directly linked to low oxygen concentrations in silicon handle. This understanding is very helpful to introduce and process new substrates in advanced front-end process flows for MOS device fabrication.

The impact of oxygen in silicon substrates and the formation of oxide precipitates have been widely investigated in the past, because of deleterious electrical recombination and their impact on yield [1]. The presence of oxygen can also be beneficial, with the so-called internal gettering effect by oxygen precipitates. More recently, researchers pointed out the role of interstitial oxygen on the formation of slip lines and dislocations [1-2]. The impact of interstitial oxygen during thermal treatments has to be distinguished from the one of oxygen precipitates for a better understanding of various phenomena [3]. We show in this paper the combined impact of features such as interstitial oxygen, thermal processes and innovating SOI substrates on slip-line generation after complex device fabrication process flows. We have investigated different kinds of silicon and SOI substrates (with silicon obtained with the Czochralski method) that were submitted to different thermal treatments during a specific 65nm process flow targeting Radio-Frequency devices. We have worked on 300mm patterned and blanket wafers and focused notably on a last stressing oxidizing anneal step used for gate oxide formation. One type of SOI substrates had a poly-silicon layer beneath the buried oxide (named SOI Trap-Rich) specifically for RF applications [4]. We have used two kinds of processes, low and high temperature, in Rapid Thermal Oxidation (RTO) tools. Slip-line counts and cumulated lengths were monitored on blanket SOI and Si wafers after main anneal steps and gate oxide RTO, using a Pattern Wafer Geometry (PWG) tool (figure 1). The post-nitridation anneal for gate oxide formation was performed at temperature above 1000°C in single wafer tools. On Si and SOI with 70nm-thick Si layers, no slip-lines were detected using Process-Of-Record conditions (whatever the process temperature). Meanwhile, high temperatures and above all extreme edge offset temperatures (usually used in single wafer reactors to have processes as uniform as possible) resulted in higher slip-line counts and cumulated lengths on the wafers back-sides. On SOI with TR layers, slip-lines were detected whatever the conditions, although they were less numerous with a low temperature and optimized process. Differences for wafers processed at the same time highlighted the influence of several parameters: the thermal history evidenced by wafer-to-wafer variability for SOI wafers with a Trap-rich layer underneath, the stack (SOI type and nature) and the process temperature used during previous oxidation steps. A typical map obtained by the PWG is shown in Figure 2 [5]. Meanwhile, Figure 3 shows a macro Photoluminescence mapping of a blanket Silicon wafer, pointing out the electrical activity of planar defects at the wafer edges (non-radiative recombination on dislocations). A direct relationship was found between the slip-line origin and contact points coming from ring supports at wafers’ back-side (the origins of slip lines). Figure 4 shows the relationship between the oxygen concentration in bulk Si and the silicon handles of SOI substrates, the slip-line counts and wafer warp. Based on this trend, we have also statistically confirmed on patterned wafers processed in a 65nm RF flow, the direct relationship between substrate deformation, low oxygen concentration in the Si handle (lower at wafer edge in agreement with slip line formation) and lithography overlay (OVL) measurements. When OVL exceeded a certain value, residuals (i.e. misalignments due to shifts between patterns which are symbolized by vectors) could not be corrected any more. It is typically what we have on SOI TR substrates with an extreme offset temperature (intentionally too high). An OVL signature out of our range of specifications is shown in Figure 5 on a patterned wafer processed up to gate oxide level. High numbers of slip lines result in OVL over detection. Meanwhile, wafer deformations and more precisely stresses that are too high increase OVL residuals. Above a given threshold, the built-in stress in the wafer is so high that slip lines are nucleated at the wafer edges to minimize the elastic energy. Above a second threshold, the wafer deformation is irreversible. Finally, the relationship between OVL and electrical failure is not straightforward and more often the consequence of mixed parameters such as substrate composition and nature, annealing steps and etching during Shallow Trench Isolation or gate oxide definition. [1] J. Fujise et al, Japanese J. of Applied Physics, 57 (035501) 2018 [2] J. Fujise et al, J. Solid State Science and Techn., 9 (055012) 2020 [3] G. Kissinger et al, J. Solid State Science and Techn., 8 (N79) 2019 [4] B.K. Esfeh et al, Solid State Electronics, 128 (121) 2017 [5] V. Brouzet et al, ASMC conference, april 2019 Figure 1

A new method to induce tensile stress in a PDSOI NMOS device for RF applications is proposed, which is based on relaxing a SiGe layer built underneath silicon. By means of TCAD simulations, we demonstrate that stress transfer from SiGe to Si occurs by means of at least two different mechanisms: SiGe relaxation due to amorphization and the formation of Stacking Faults during recrystallization. By considering both phenomena, a tensile stress of 0.5 GPa can be injected into the silicon channel. Moreover, the impact of annealing steps on the detrimental out-of-SiGe Ge diffusion has been simulated by considering an inter-diffusion model, showing the importance of adapting the PDSOI process flow to account for the presence of the new stressor.

Hot carriers injection (HCI) degradation plays an important role in advanced technologies. We carried out an extensive analysis of this degradation mode on 55nm MOS transistors and showed that for large channel lengths, a stress at V-G = V-D becomes more critical than at V-G = V-Gibmax condition. This is imputable to an additional degradation mechanism distributed throughout the channel, which likely appears on nitrided samples.

In this paper, the reliability of thick SiO2 gate oxides is assessed using quasi-static and multi-frequency capacitance measurements after constant current stress. A comprehensive study of oxide wear-out is presented, highlighting trapping mechanisms and switching states generation occurring during stress at high electric fields. Measurements are performed on furnace grown and HTO-based oxides and the correlation with lifetimes extrapolated from time-dependent dielectric breakdown is discussed.

The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to today's technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 Å to 150 Å range grown with oxidation temperatures between 850 and 1100 °C were targeted. The present work shows first that for all investigated processes, oxidation follows a parabolic regime even for thin oxides, which indicates a diffusion-limited oxidation regime. We also observe that, for all investigated processes, the SiGe oxidation rate is systematically higher than that of Si. The amplitude of the variation of oxidation kinetics of SiGe with respect to Si is found to be strongly dependent on the process type. Second, a new quantitative analysis methodology of oxidation kinetics is introduced. This methodology allows us to highlight the dependence of oxidation kinetics on the Ge concentration at the oxidation interface, which is modulated by the pile-up mechanism. Our results show that the oxidation rate increases with the Ge concentration at the oxidation interface.

Ultrathin compressively strained SiGe layers is one of the most promising materials for high mobility channels of p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFETs). Fabrication of such layers as well as formation of high-quality gate oxides on SiGe both involve SiGe thermal oxidation processes. These processes require well-controlled oxidation kinetics and oxide properties. This work discusses oxidation kinetics of SiGe in light of the characterization of the thermal oxide density by the Resonant Soft X-Ray Reflectivity (R-SoXR) technique.

Targeting the integration of embedded non-volatile memories on thin-silicon body technology, high temperature oxide (HTO) is evaluated on a 40nm automotive eFlash process as replacement of furnace grown thick gate oxide for high voltage transistors. Different thermal treatments are evaluated to enhance HTO quality, including growth of interfacial layer, reoxidation and high temperature annealings. Transistor performance and reliability are thoroughly studied, showing that the main challenge for HTO integration is time-dependent dielectric breakdown. Because of higher charge trapping, HTO is found to be less reliable than grown oxide. However, optimized dedicated treatments successfully improve HTO quality and reliability.

The demand for higher speed and lower power consumption ICs has motivated research for higher mobility channel materials (1). Compressively strained SiGe is known to feature higher hole mobility than Si and is largely compatible with the Si CMOS manufacturing platform. Besides, the FDSOI transistor architecture allows power consumption reduction (2), thus making SiGe-On-Insulator (SGOI) channels promising. SGOI layers can be fabricated by the so-called condensation technique, which is based on concurrent Si selective thermal oxidation of SiGe and SiGe composition homogenization by Si and Ge interdiffusion (see Figure 1) (3). Therefore, a sound understanding of kinetics of oxidation and interdiffusion of SiGe is required to develop optimized SGOI structures. SiGe dry oxidation rate has been reported to be higher (4) than or equal (5)(6) to the one of Si. It therefore remains unclear. Few groups investigated Rapid Thermal Oxidation (RTO) (4) while most of them looked at furnace oxidation. Moreover, most studies only considered the initial Ge content to compare oxidation kinetics. Indeed, the Ge concentration below the SiGe-oxide interface is strongly varying with time because of two mechanisms: firstly, the Si-selective oxidation of SiGe tends to pile-up Ge below the oxidizing interface; and secondly, interdiffusion of SiGe favors homogenization of the layer (6). This paper focuses on the oxidation rate of SiGe in regards to the varying Ge concentration in the SiGe layer for various oxidation conditions. Thick (> 20 nm) SiGe layers with either 10% or 30% Ge concentrations were epitaxially grown on bulk Si wafers. Oxidation was performed by RTO in 1 atmosphere of pure O2, with different oxidation temperatures and durations. Oxide thickness and SiGe composition versus depth were measured by Spectroscopic Ellipsometry and X-Ray Reflectivity, and by Secondary Ion Mass Spectroscopy respectively. Figure 2 shows the Ge concentration profile below the oxide. A rapid creation of a pile-up layer is observed at all temperatures. Then, three regimes of evolution of the pile-up layer are distinguished: the Ge concentration at the oxidizing interface (a) increases, (b) is constant, and (c) decreases. The regime of evolution of the pile-up layer is determined by a competition between the oxidation speed and the interdiffusion speed. As schematically illustrated Figure 3, the interdiffusion speed overcomes the oxidation one at higher temperatures because the activation energy of interdiffusion in SiGe ([4,5] eV (7)) is well above the one of SiGe oxidation ([2,2.6] eV (4)). Phrased in a different way, the temperature dependence of interdiffusion is higher than the oxidation one. Figure 4 shows the oxide thickness versus the oxidation duration for dry RTO at 900°C, 1000°C and 1100°C. A higher oxidation rate is observed for SiGe compared to Si for all temperatures. Then, to highlight the effect of the Ge concentration at the oxidizing interface, we fitted the curves to extract oxidation rates for each oxidation conditions. We define the Growth Rate Enhancement (GRE) as the ratio of the oxidation rate of SiGe to the one of Si at a given oxide thickness and for identical oxidation conditions. It is indeed important to highlight that comparing oxidation rates at the same oxide thickness is mandatory: if we want to examine the effect of Ge on the oxidation rate, we have to take into consideration the fact that the oxidation rate also decreases with the oxide thickness. Such an approach allows us to freeze the system and to find more easily correlations. We report on Figure 5 four GRE values extracted from our data versus the Ge concentration at the oxidizing interface. We thus observe that the higher the Ge concentration at the oxidizing interface is, the higher the GRE tends to be. We thus showed that Ge redistribution by interdiffusion during SiGe oxidation can follow different regimes. We also evidenced that for dry RTO conditions, the higher the Ge concentration at the oxidizing interface is, the higher the GRE is. Understanding the interdependence of these two mechanisms is essential to get an accurate picture of the condensation process. Therefore, data for dry RTO will be completed and an in-depth discussion will be led. A similar study will also be conducted for a wet oxidation process called In-Situ Steam Generation (ISSG). (1) Pillarisetty, R., Nature 479.7373 (2011): 324-328. (2) Weber, O., et al., VLSIT IEEE, 2014. (3) Tezuka, T., et al., JJAP 40.4S (2001): 2866. (4) Spadafora, M., et al. MSSP 8.1 (2005): 219-224. (5) LeGoues, et al., APL 54.7 (1989): 644-646. (6) Long, E., et al., PSS (a) 209.10 (2012): 1934-1939. (7) Kube, R., et al., JAP 107.7 (2010): 073520. Figure 1

SiGe-On-Insulator layers are promising materials for high mobility pMOSFET channels and can be fabricated by the condensation technique. This technique is based on SiGe oxidation and a sound understanding of it is thus needed in order to fabricate optimized SGOI structures. The present study is a read-across of oxidation kinetics and Ge redistribution during dry Rapid Thermal Oxidation (RTO) of SiGe layers with different compositions and different oxidation temperatures. The evolution of the Ge concentration below the oxidation front is found to follow different regimes depending on the oxidation temperature. We examine them in light of a competition between oxidation rate and diffusion rate. It is also shown that RTO of SiGe is faster than Si and that the oxidation rate depends not only on the initial Ge concentration, but also on the oxidation temperature. A correlation between the Ge concentration below the oxidation front and oxidation kinetics is evidenced.

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

Ge condensation using RTO is investigated to produce good quality SGOI channel. This study shows the significant role of the RTO temperature in Ge condensation. First, Ge diffusion requires a RTO temperature above 950°C to start homogenization of Ge in the channel. This is mandatory to minimize the risk of defects generation. Then, inconsistently to thermodynamics calculation, Ge-O bounds are formed during oxidation and a higher temperature oxidation leads to a lower Ge-O bounds formation. Therefore, Ge condensation using a 1100°C RTO is preferred. It is implemented in a SOI/SGOI co-integration to produce SGOI channel for PMOS transistor. Such channel exhibits a very smooth surface (RMS roughness below 0.15nm), a controlled Ge content (16%) and a high compressive strain (1%). Moreover, PMOS Vt modulation by the Ge concentration was performed with a sensitivity of 10mV/%. As a result, this study demonstrates that RTO is a solid alternative to furnace for Ge condensation.

High mobility channels are considered as an interesting path to increase PMOS performances for advanced CMOS technology. Silicon-Germanium On Insulator (SGOI) benefits from both the advantage of the SiGe material (hole mobility booster) and the On Insulator structure (better electrostatic control of the channel by the gate) [1]. The co-integration of NMOS and PMOS, respectively on Silicon On Insulator (SOI) and SGOI zones, can be enabled easily by the Ge condensation technique [1,2]. This technique is based on the competition between Ge diffusion and Si oxidation which are both driven by temperature. For this purpose, mainly furnace oxidation is reported in the literature [1-3]. In this work, we propose to study Ge condensation using Rapid Thermal Oxidation (RTO) as an alternative process. SGOI structures were fabricated on 300mm SOI wafers, with 11nm thick top silicon. First, epitaxy layers of SiGe were grown with varying thickness (from 3 to 10nm) and Ge concentration (from 10 to 40%). The SiGe film was grown by Rapid Thermal Chemical Vapor Deposition at temperature between 600°C and 650°C. Then, Ge condensation was performed by RTO in O 2 ambient at temperatures between 950°C and 1150°C. Both aspects of Ge condensation were studied: Ge diffusion then Si oxidation. The RTO temperature effect on Ge diffusion was analysed by ToF-SIMS (Figure 1). In the case of short oxidation duration (below 2 minutes), as typically used in RTO compared to furnace (several hours), almost no diffusion is observed at 950°C. This leads to Ge enrichment of the initial SiGe layer with Ge concentration gradient. For longer oxidation, this might result in very high Ge concentration generating strain relaxation via stacking fault creation [4]. Therefore, temperatures above 950°C are prefered to avoid defects creation. TEM and STEM-EDX of the structure after condensation (Figure 2) shows that Ge concentration is still not totally homogeneous at 1100°C. Oxidation kinetics is shown on Figure 3, comparing the effect of substrate: SiGe/Si/BOX vs Si. SiGe is oxidized faster than Si, as already reported [5,6]. Moreover, SiGe oxidation is enhanced with increasing Ge concentration. Same trend is observed concerning SiGe thickness, indicating the effect of Ge diffusion in the underneath Si layer. A compositional analysis of the oxide grown by condensation was performed by XPS, monitoring the Ge3d peak (Figure 4). Starting from the same SiGe/Si/BOX structure, the oxide thickness was kept the same using different RTO temperatures but tuning the O 2 pressure and the RTO duration. The effect of Ge diffusion is clearly observed by the intensity of the Ge-Si contribution. Higher temperature leads to lower Ge concentration due to a more homogeneous Ge distribution. Surprisingly, Ge-O bounds are also observed, whereas Si x Ge 1-x alloy oxidation is thermodynamically considered to be Si selective [7]. Moreover, the amount of Ge-O bounds increases when the RTO temperature decreases. As shown previously, low temperature oxidation leads to high Ge concentration at the SiO2/SiGe interface, which may enable the formation of Ge-O bounds [8]. As a consequence, oxidation kinetics plays an important role in this phenomenon. This study reveals the significant role of temperature in Ge condensation by RTO. Due to kinetics effect, Ge-O bounds are formed which is not predicted by thermodynamics. Finally, the role of temperature will be investigated through electrical characterization of the Si x Ge y O properties. [1] B. Vincent at al, Mat. Sc. Semicond. Proc. 11, 2008 [2] T. Tezuka et al., Jpn. J. Appl. Phys. 40, 2886, 2001. [3] Z. Di et al., J. Crystal Growth 281, 2005 [4] B. Vincent, Appl. Phys. Lett. 90, 2007 [5] O. W. Holland et al., Appl. Phys. Lett. 51, 7, 1987 [6] S. J. Kilpatrick et al., J. Appl. Phys. 81, 12, 1997 [7] D. C. Paine et al, J. Appl. Phys. 70, 5076, 1991 [8] J. Eugene, Appl. Phys. Lett. 59, 78, 1991

Recently, great improvements have been obtained on Chemical Vapor Deposition (CVD) processes and their integration in advanced MOS technologies. Actually, Si and SiGe materials realized by CVD processes are excellent candidates to provide technical solutions what ensure the continuing device performance enhancement. This work reports an extensive investigation regarding the anisotropic effects observed when Si and SiGe films are grown by CVD processes on various Si surface orientations. To focus as possible, our study on intrinsic and fundamental growth parameters, simple hydride chemistry was used for the different depositions. In this case, we have first observed that the film morphology and the film thickness strongly depend on the surface orientation. Then, we have characterized the anisotropy of the growth kinetics and proposed a model explaining its origin in our experimental conditions. This model is based on surface structure and dangling bond density considerations and, for a simple deposition illustrated by the Si epitaxy this model seems to explain the root cause of faceting appearance. Finally, compared to Si material, the SiGe hetero-epitaxy is found to be more sensitive to the anisotropic effects. Therefore, we supposed in this latter case, the influence of others mechanisms, such as mixing or growth modes.

A fabrication method for silicon beams and membranes defined in lateral and vertical dimensions, as well as superposed silicon membranes, all realized in bulk silicon using only one lithographic step is proposed. This proposal is based on observations made on structures obtained by High Temperature Annealing (HTA) in hydrogen atmosphere process. The combination of design configuration and materials technology (hard mask) with the process shows the possibility of new 3D devices and cavities beyond previously reported capabilities of with this technique. The specific design and hard mask engineering presented can lead to structures used in a bulk silicon platform for 3D devices with optical and electronic functions for the fabrication of bulk silicon waveguides and transistors on stressed membranes with enhanced mobility.

Facet apparition during selective epitaxial growth of silicon and silicon–germanium alloys is reported in terms of morphology and kinetics. Epitaxial growth was performed on (001) Si wafers by chemical vapour deposition using the H2/HCl/SiH2Cl2 chemistry for silicon and GeH4 addition for silicon–germanium alloy. The (001) Si and SiGe growth rate was found to be limited by chlorine desorption at low temperature. The creation and development of (311) facets has been clearly explained by the epitaxial growth kinetics considerations. The impact of the deposition conditions, of the pattern structure and also of the dielectric nature on faceting are discussed here and analysed, thanks to cross section scanning electron microscopy (XSEM) and cross section transmission electron microscopy (XTEM) observations.

A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing (HME-HTA) in hydrogen ambiance is reported The use of a nitride/oxide double hard mask stack on silicon during the etching of bulk structures allows for leaving a patterned nitride thin film on the structures surface during the high temperature annealing, after having removed the top oxide layer. This solution will be referred as the nitride-capped approach, which is an alternative to the use of a single sacrificial oxide hard mask for a free Si surface annealing (referred as the mask-less approach). The nitride-capped approach opens new technological and design possibilities when using 2D arrays of various geometry trenches. Implications and potential device applications are discussed, such as the role played by the silicon-nitride interface during the annealing process, the role of the remaining nitride layer, and the possibility to explore this 3D technique to solve the planar independent double gate transistor challenge.

This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint W design . We compare the fabrication between <110> channel, i.e. non-rotated wafer, and <100> channel, i.e. 45deg-rotated wafer, for the same (100) surface orientation.