Security is an important driver for the evolution of the RISC-V architecture. Several initiatives aim at exploiting the privileged architecture and the Physical Memory Protection mechanisms foreseen by the RISC-V specification as a foundation for robust trusted execution environments. This short paper introduces a memory encryption unit fitting the organization of the RISC-V privileged architecture. The unit is suitable for very resource-constrained systems and is mainly targeted at FPGA devices. The design relies on a flexible and efficient stream cipher, the ChaCha algorithm. The work presents an overview of the system architecture and the detail of the FPGA-based implementation of the memory encryption unit, along with some experimental evaluation and comparisons with state-of-the-art contributions.
This paper proposes the re-design of the functionalities of the personal care robot (PCR) Pepper by SoftBank Robotics. Pepper is mainly designed for verbal interaction with patients and despite the presence of two upper arms, it lacks object manipulation capabilities. In the proposed re-design, a combination of data from Pepper RGB camera and 3D depth sensor is used to identify and localize a specific pharmaceutical envelope in a dedicated repository. In this context, the semantic segmentation of the RGB image has been entrusted to a dedicated pretrained YOLOv3 object detector, while a dedicated algorithm has been realized for the hand (gripper) positioning. Basing on this 3D positional information, the PCR operates an ad-hoc designed routine to grasp the object and to scan it. Once the scanning procedure confirms that the grasping has been successfully completed and that the grasped package matches with the needed drug, the PCR must be able to safely navigate towards the user (e.g., physician, patient), delivering the drug. The proposed procedure is fully automatic, and no internet connection is needed for the nominal use case, preserving -in this way- sensitive data like home/hospital maps, patient’s data and so on. Experimental results on the here proposed object manipulation routine demonstrated a grasping success rate up to 96 %, even if the objects are not properly positioned in the dedicated repository. Finally, a proof of concept that implements a sequential pick-up, object recognition and delivery operation is also provided demonstrating real-life scenario applicability.
Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory’s quality: they can cause random read outputs, which might lead to test escapes and no-trouble-found devices later when the device is already in the field, as well as compromise the circuit’s quality by reducing the memory cell’s Static Noise Margin (SNM). Therefore, the detection of USF is critical. This paper proposes a test solution to improve the detection of USFs in FinFET SRAMs. To achieve this, we first analyze the impact of USFs on the cell’s SNM and bitline swing during read operations. Then, we perform an experimental study of stress conditions’ (SCs) impact on sensitizing and detecting USFs. Finally, we propose a dedicated Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults. This scheme introduces a small area overhead while significantly improving USF detection. Hence, using the proposed DFT leads to fewer test escapes and higher-quality FinFET SRAMs.
Side channel attacks are a serious threat to integrated circuits. They are hardly detectable and use inherent information leaked by the hardware to infer sensitive information like secret keys. Over the last ten years, numerous side channel attacks have been examined, exploring various forms of leakage channels such as time, power, electromagnetic field, photon emission, and acoustic. Among them, power side channel attacks are the most popular ones. Developing an appropriate counter-measure against such attacks requires a deep understanding of these attacks. This paper presents a study of the most popular power attacks such as differential power attack and correlation power attack and discusses the latest countermeasures in this domain and their shortcomings.
Systems for harsh environments often use embedded processors for tasks that require reliability. However, harsh environments cause faulty behavior in electronics, which eventually lead to system failure. Therefore, embedded processors must use techniques to improve their reliability. In this context, this work presents the implementation and characterization of a RISC-V-based system-on-chip. We characterized our implementation by carrying out test campaigns at the ChipIr irradiation facility. This facility provides a beamline for testing electronics against neutrons, mimicking atmospheric-like environments. With this first test campaign, we identified the most critical parts of our system-on-chip and essential tips to improve the test effectiveness. In the second test campaign, we used an improved version of the system setup with higher reliability error observability features. The version embedding all the hardening techniques could correct or mitigate 98.1 % of the detected upsets under irradiation.
The complexity of heterogenous Systems-on-Chip has overgrown in the last decades, and the effort necessary to set up a verification workflow has increased as well. The time spent on the verification phase of a design takes on average 57% of the project time, and in these years, several solutions aimed to automate that task have been developed. Some relevant works in this field automate the VLSI design flow from synthesis to Place-And-Route and Layout-Vs-Schematic design check but miss software design in the automated verification loop. Our work focuses on the early stages of the design phase, where designers take software and hardware choices to explore a larger design space. In this work, we present a flexible, Make-based framework to build up verification and design environments. It aids the development of Systems-on-Chip running RISC-V processors, automating software compilation, cycle-true simulations and post-synthesis analyses. It exploits the parallelism of the Make build tool to ensure results consistency, provide flow reproducibility, and accelerate the design space exploration using different flow recipes provided by the designer. Its modular structure allows it to perform each task with various third-party tools and makes the workflow execution chain customizable. Using the proposed framework, we show how the reduced designer effort increases design productivity. Indeed, the time needed to build up a validated development environment is consistently reduced by using few configuration properties to setup all the tools used in the workflow.
This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor.
This paper presents a high-resolution Class-C type voltage-controlled oscillator (VCO) with a robust start-up. The proposed oscillator achieves a minimum frequency quantification step of 270 Hz without adding any additional dithering approach. The very fine tuning is obtained through a capacitive-inductive degeneration coupling (CIDC) technique which reduces the capacitance value without appreciably affecting the intrinsic oscillator phase noise (PN). This technique also provides a negative transconductance to compensate for losses in the LC tank, resulting in high oscillation amplitude and relatively low power consumption in the oscillator core. The proposed design, implemented in 130 nm CMOS technology, achieves 45% tuning range. It exhibits a phase noise of -107 dBc/Hz @ 1-MHz offset, while it draws 5.75 mA from a supply of 1.2 V, resulting in a FoM of 165 dBc/Hz.
This paper addresses the design and characterization of different architectures of novels high-density multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.
This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets, examining testability of our processor, or developing test procedures for it. We first choose our CUT as a version of RISCV and explain its ISA and eventually its RTL architecture. Various test techniques for this processor are studied, and then we will choose the IEEE Std.1149.1 for insertion into our processor and developing a virtual tester to interact with the test-ready processor model.
Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.
The Electrically Erasable Programmable Read Only Memory (EEPROM) technology has been widely studied but EEPROM Technology Computer Aided-Design (TCAD) simulations still need to be improved to handle the rises of the quality requirements of the semiconductor market. In this paper, the impact of endurance degradation on EEPROM programming window and the corresponding TCAD simulation are investigated. Advanced calibrated TCAD simulation on 110nm node is used to evaluate the distribution of negative charges trapped in the tunnel (bulk) oxide during EEPROM cycling. The total negative charge evolution found by our simulation is in agreement with the well-known trapping power law found in the literature.
Software Hardening against memory safety exploits can be achieved from the silicon, up to the software, with both compilers and operating systems features. Unfortunately, due to the growing evolution of attacks, security architects have no guarantees, at an early stage of the development, that defenses will match the security needs and overcome the targeted threats. In addition, after product release, it is difficult to evaluate the architecture performance against new threats. This paper presents a dynamic analysis technique that allows the evaluation of the security profile of a given architecture during design exploration. The method is designed to highlight and quantify the security threats covered by the countermeasures embedded at any level of a given architecture. The provided results will help for protection evaluation, classification, and architecture choices. The method comes with a tool that implements this approach and has been applied to several architectures. This tool helps to classify architecture along with its alternatives thanks to metrics.
Emerging non-volatile memories are getting new interest in the system design community.They are used to design logic-in-memory circuits and propose alternatives to von-Neuman architectures.Hafnium oxide-based based ferroelectric memory technology, which is fully compatible with CMOS technologies is particularly interesting for logic-in-memory designs.Indeed, this compatibility leads to various possibilities for fine-grain logic in memory applications where the memory capable element is tightly integrated with the transistors in the system.Nonvolatile and energy efficient computing for Internet of things and embedded artificial intelligence are among the potential applications for this technology.In this article, we focus on ferroelectric field-effect transistors (FeFET) and present an overview of three different fine-grain logic-in-memory possibilities with FeFETs: custom operation designs, reconfigurable circuits and a hybrid memory element accessible by content or by address.All presented circuits have been designed within a test chip using 28nm technology provided by GLOBALFOUNDRIES.
This work reports on the design and optimization of a low voltage shunt MEMS switch for 5G mobile applications. As opposed to clamped-clamped beams conventionally serving as RF-MEMS shunt switches, the present switch design utilizes a fixed-free cantilever beam in a shunt configuration to minimize the actuation voltage requirements. Moreover, RF performance parameters (ON-state insertion loss and OFF-state signal isolation) for the proposed switch design are optimized by means of extensive high-frequency simulations to enable the use of such devices in mm-wave regime. To critically analyze the key controlling factors affecting switch performance, a parameterized study on the geometrical parameters of the proposed topology is performed. The simulations were carried out using commercially available finite element solvers (CoventorWare® and HFSS) which validate the low-voltage operation of the reported switch with actuation voltage as low as 7.5V while maintaining the RF insertion loss and RF isolation values below -0.3dB and above -36dB, respectively, for frequencies up to 45GHz.
Nowadays, the modern electronic systems are facing an important limitation in terms of performance, known as von Neumann bottleneck. It affects the communications between two crucial elements, the CPU and the memory, which suffer from a saturation in bandwidth. Many solutions are currently under investigation and among them the concept of Logic-in-Memory (LiM) has been introduced: a memory enriched in its array of computational elements which enable the implementation of a flexible distributed processing system. The current work introduces Octantis, a High-Level Synthesizer useful for the exploration of LiM architectures. The proposed software analyzes an input algorithm described in standard C language and identifies which LiM architecture would implement it better. At its output, the synthesized solution is provided together with a test-bench, to properly characterize it, in terms of performance, spatial occupation and power consumption. Many algorithms have been successfully synthesized by Octantis and some of the results achieved will be discussed along the document.
Emerging non-volatile memories are widely studied today as means to maximize energy efficiency and because they enable the so-called Computation-In-Memory. The Logic-in-Memory (LIM) paradigm is a subset of the Computation-in-Memory and it focuses on the execution of Boolean operations inside the memory. Among the most popular solutions, MAGIC and FELIX promise non-input destructive operations, as classical computation paradigms, allowing therefore to re-use the set of input data for several operations. In this paper we have analyzed the electrical behavior of some significant LIM implementations (MAGIC NOR and FELIX NAND) under various operation conditions. Our results show that it is not trivial to guarantee noninput destructive operations (in the case of FELIX NAND) and there is a real difficulty in concatenating several operations due to non-ideal intermediate results.
Massive multisite testing significantly reduces test cost and immensely increases production throughput by simultaneously screening multiple devices under test (DUTs). However, non-trivial variations in measurement from site to site are inevitable, and they often alter the actual DUTs specifications leading to yield loss (good DUTs rejected as bad) or necessitate poorer DUT specifications. These site-induced variations make it challenging to know the true silicon performance in a multisite probing environment, making statistical processing control difficult. In this paper, we propose and compare three methods to remove the variability introduced by multisite test hardware for accurate estimation of DUTs true performance distributions. The key idea is to select high confidence good test sites for parametric analysis. We demonstrate the accuracy of the proposed methods using simulation and measurement data.
In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.
The IEEE 1687 Std. provides an efficient access methodology for embedded instruments in complex system-on-a-chip designs by introducing reconfigurable scan networks. This flexibility enables the reduction of the overall test access time, which significantly decreases the test costs compared to the conventional daisy-chaining method. However, the new access methodology strictly requires effective test schedulers that consider multi-power domains with individual constraints.This work proposes a novel test scheduler that orchestrates the Boolean Satisfiability problem in conjunction with Pseudo-Boolean optimization techniques. The effectiveness of the proposed scheduler is proven by considering networks with over one thousand of so-called instruments forming industrial representative benchmark candidates.
