3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

The introduction of TSVs is a major change of paradigm, which electrical impact on circuit functionality has to be carefully investigated. Specific test structures dedicated to characterize the substrate noise transfer function between aggressor TSVs and sensitive MOS transistors (N or P) were designed. For the first time, TSV to MOS gate and drain couplings were characterized through scattering parameter measurements up to 40 GHz. Substrate attenuation of perturbation generated by TSV increases from -60 dB to -20 dB with frequency. Coupling mechanism strongly depends on the MOS transistor state, up to 10 dB in difference being observed between ON and OFF. Coupling transfer function according of MOS transistor type is also extracted considering N, P, and isolated N MOS. Electrical coupling mechanism and dependency are explained through MOS to substrate coupling models, based on semi-conductor theory, enabling noise-based 3D design for future circuits

In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2 μm diameter and 15 μm of depth. Thermal cycling and electromigration stresses are performed on dedicated devices. Thermal cycling is revealed to induce only defects on non-mature processes. Electromigration induces voids in adjacent metal level, right at TSV interface. Moreover, the expected lifetime benefit by increasing line thickness does not occur due to increasing dispersion of voiding mechanism. Second part covers reliability of Cu TSV-middle technology, of 10 μm diameter and 80 μm depth, with thermal cycling, BEoL dielectric breakdown, and electromigration study. Thermal cycling is assessed on two designs: isolated and dense TSV patterns. Dielectric breakdown tests underline an impact of TSV on the reliability of metal level dielectrics right above TSV. Electromigration reveal similar degradation mechanism and kinetic as on TSV-last approach.

Some 3D interconnects technologies are reviewed and discussed in this paper with respect to emerging 3D applications. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, the very fine pitch below 10μm will be mandatory for 3DIC and many options like cu-cu bonding or μ-tubes are in the race. Specific interconnects for RF/mm-waves and low volume electronics devices are also discussed with relevant examples.

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

This paper proposes studies to learn more about substrate coupling phenomena in 3D-IC by evaluating their impact on signals integrity. Studies consist in analysing analogue signals and realistic digital communications while respectively RF or high speed signals are carried by interconnections such as TSV and RDL in noisy environment. Integrity of transmitted signals is analyzed in terms of signal amplitude, signal shape, SNR (signal to noise ratio), data rate and eye diagrams when a chosen parasitic signal plays the role of noise.

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.

This paper reports the use of SAM (Self Assembled Monolayer) formation to deposit the copper diffusion barrier into high aspect ratio TSV. SEM, AFM, water contact angle and zeta potential techniques have been used to better understand the surface functionnalization. Adhesion tape tests and SIMS analysis have been performed on Cu/NiP/SiO2/Si coupons showing no limiting issue for further integration. Our results on TSV demonstrate the feasibility of wet process to get super conformal barrier deposit into high aspect ratio TSV.

In new circuits performed with 3D integration technology, electromagnetic interference through stacked silicon substrates may occur due to signals propagated in Through Silicon Vias (TSV) and along Redistribution Layers (RDL). So, to optimize electrical performances of these new 3D digital or RF circuits, substrate coupling effects need to be characterized, modeled and quantified in a large frequency bandwidth. In this paper, we mainly analyze substrate coupling effects using dedicated capacitive test structures These structures are characterized using aggressive RF or high speed signals propagated along Through Silicon Vias (TSV). These RF or time domain signals in TSV are used to generate parasitic noise signals in silicon substrates. By analyzing the extracted results, solutions will be proposed to reduce this substrate noise.

This paper focuses on the EM induced voiding in a line ended by a TSV, and proposes an analytical model based on the link between the monitored electrical resistance increase and the matter depletion flow.

Developments in 3D integration technology reveal several basic interconnect elements, as Through Silicon Via, Redistribution Layers, Cu-Pillar and bumps to transmit signals inside 3D circuits. Impact of the interconnect elements on high speed signal integrity all along the global 3D interconnection chain requires investigation. First each element was successively characterized and an equivalent electrical model was extracted in the frequency domain from measurements or simulations. Next these models were realistically chained to simulate the signal integrity performance, declined as delay, of the global 3D-IC interconnection chain in order to determine the best strategies among the multitude of options involved in 3D integration. Three studies were investigated in detail regarding routing strategy, the choice of chip stack orientations (Face-to-Face or Face-to-Back), and the comparison of various 3D technologies available, resulting in global recommendations for future 3D products.

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.

This paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV), and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (EM) tests. Physical analyses reveal the presence of a carbon impurity layer at bottom of the higher resistance TSVs. This impurity induces failure during TCT, but has no impact on EM time to failure distribution. We also discuss the relevance of different electrical resistance failure criterions after TCT for a single TSV.

4 mu m wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7 mu A/mu m on the static NMOS drain current. However, the ring oscillators response is not impacted.

Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to improve heterogeneous 3D chip performance in the frame of a "more than Moore" approach. Accurate modeling of TSV is consequently essential to perform design optimizations and process tuning. This paper proposes a methodology based on RF characterizations and simulations, leading to a frequency dependent analytical model including MOS effect of high aspect ratio TSV. Specific test structures integrated on both floating Si bulk and CMOS 65 nm active wafers according to a face-to-face Via Last After Bonding process enable C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) and implemented in SPICE simulator to predict TSV impact on signal propagation.

Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material and process optimizations. This paper presents a frequency dependent analytical model including MOS effect of high aspect ratio TSV achieved in a full CMOS 65 nm platform according to a face-to-face Via Last process. Specific test structures with bulk contacts to polarize silicon were integrated enabling C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed and simplified according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) leading to a full analytical model.

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3μm wide and 15μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.