A promising candidate to selectively etch silicon against dielectrics is here studied. This paper reports a detailed study of the silicon chemical vapor etch with HCl/H 2 mixtures. Kinetics measurements on (001)-oriented wafers permitted us to extract apparent activation energies varying from 95.2kcal/mol and 73.9kcal/mol, depending on the HCl dilution in the chamber. On the other hand, etch rate measurements as a function of the HCl partial pressure are found to follow a sub-linear behavior indicating complex mechanisms occurring with the use of the HCl/H 2 gas mix. In a second part, thanks to SEM cross-section observations, morphological analysis permitted us to point out that the {311} facet behaves differently as compared to the {111} and {100} planes. To conclude, we extracted rugosity data after HCl treatment from Atomic Force Microscopy (AFM) measurements and all these results permitted us to validate the potential industrialization of this etching process for the formation of localized cavities or junctions on patterned wafers.

The very significant growth of the wireless communication industry has spawned tremendous interest in the development of high performance radio frequencies (RF) components. Micro electro mechanical systems (MEMS) are good candidates to allow reconfigurable RF functions such as filters, oscillators or antennas. This paper will focus on the MEMS electromechanical resonators, which show interesting performances to replace surface acoustic waves (SAW) filters or quartz reference oscillators, allowing smaller integrated functions with lower power consumption. The resonant frequency depends on the material properties, such as Young’s modulus and density, and on the movable mechanical structure dimensions (beam length defined by photolithography). Thus, it is possible to obtain multi frequencies resonators on a wafer. The resonator performance (frequency, quality factor) strongly depends on the environment, like moisture or pressure, which imply the need for a vacuum package. This paper will present first resonator mechanisms and mechanical behaviors followed by state of the art descriptions with applications and specifications overview. Then MEMS resonator developments at STMicroelectronics including FEM analysis, technological developments and characterization are detailed.

A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing (HME-HTA) in hydrogen ambiance is reported The use of a nitride/oxide double hard mask stack on silicon during the etching of bulk structures allows for leaving a patterned nitride thin film on the structures surface during the high temperature annealing, after having removed the top oxide layer. This solution will be referred as the nitride-capped approach, which is an alternative to the use of a single sacrificial oxide hard mask for a free Si surface annealing (referred as the mask-less approach). The nitride-capped approach opens new technological and design possibilities when using 2D arrays of various geometry trenches. Implications and potential device applications are discussed, such as the role played by the silicon-nitride interface during the annealing process, the role of the remaining nitride layer, and the possibility to explore this 3D technique to solve the planar independent double gate transistor challenge.

This chapter focuses on the developments of silicon–germanium and silicon–germanium– carbon epitaxies by rapid thermal chemical vapor deposition (RTCVD) and their integration in complex technologies. It presents the RTCVD technique in terms of equipments and process capabilities for SiGe epi. The chapter discusses the important points of the Si-based alloy epitaxy: surface preparation, low-temperature epi (LTE), germanium and carbon incorporation, and selective epi. LTE is usually obtained with hydrides like silane- or chlorides-like dichlorosilane. The chapter illustrates the RTCVD capabilities giving a few examples of current applications developed at STMicroelectronics. It explains the selection is very limited: epitaxial base of heterojunction bipolar transistor, epi for gate-all-around MOS and epi on ultrathin silicon on insulator films. In addition to that, ultrathin Silicon on insulator with an improved electrostatic integrity should dramatically improve short-channel effects that are important issues in advanced digital complementary metal oxide semiconductor with ultrashort channels.

Since the introduction of Germanium in Silicon Bipolar transistors, and more recently the introduction of Carbon, the base bandgap of SiGe:C heterojunction Bipolar transistors have been engineered to enhance device performance, thereby making them suitable for a wide range of high speed analog and RF applications

In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni2Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxides

Faceting is for a long time a fundamental concern in crystal growth. Macroscopic crystal shape studies and the Wulff theorem even founded crystal physics [1]. However, as compared to the equilibrium shape of crystals, faceting is a much more complex mechanism: it very often relies on kinetics phenomena and depends then on process conditions; it has also to be considered in very various system configurations, i.e. different geometries and different materials. In silicon technology, selective epitaxial growth (SEG) is a nice example where faceting may be an important characteristics in applications such as elevated sources/drains, MOS channel formation... Faceting is also observed in some etch pit features, one well-know example in Si being the KOH wet etching that systematically produces {111} facets. In this contribution, based on recent results, faceting effects in both epitaxial deposition and etch process will be illustrated and discussed. All the results reported here were obtained applying epitaxy or etching on patterned wafers, and SEM cross-section observations. Epitaxy and etching were both performed on (001) Si wafers using an industrial rapid thermal chemical vapor deposition (RTCVD) reactor, and with the standard chemistries HCl/H2 and SiH2Cl2(GeH4)/HCl/H2, respectively. In the case of epitaxy, in order to easily observe the facet evolution and morphology thin SiGe (Si) markers were introduced in the Si (SiGe) deposition and were submitted to Aragona delineation before cross-section observation. Spacers were chosen thin enough to be expected not impacting too much the facet behavior. The measured angles of facets allowed their identification and the measured thicknesses gave their deposition kinetics. Silicon SEG facets Faceting is observed for a long time in Si SEG [2], and most of the studies are targeting the facet suppression or reduction. However, a global view is rarely reported. Clearly, the presence of specific facets, i.e. {111}, {311}, {911}... depends on the process conditions and sample configuration [3]. Fig. 1 reports the morphology of silicon SEG deposited between SiO2 walls using two different temperatures. At 850°C, {311} facets that are created at the SiO2 wall propagate rapidly in such a way that the (100) plane is even completely occluded from the fourth Si film on. At 750°C and for similar thicknesses, no {311} facets are observed and epitaxy takes place on the (001) plane all along the process: faceting is suppressed. Fig. 2 reports the Si morphology obtained with another sample configuration. In this case, the process is very similar to that used in Fig.1 but epitaxy takes place on a silicon surface that presents some relief. In such a case, at 750°C we observe the propagation of large {111} facets; note they were absent in Fig. 1.b. On the contrary, at 850°C the {111} facets vanish very rapidly allowing appearance and development of {311} facets to join the two (001) surfaces. Again, besides the sample configuration, the deposition temperature with associated kinetics mechanisms is the key factor of facet selection and propagation. SiGe SEG facets SiGe SEG presents some unique advantages as compared to Si, however its faceting behavior is somewhat different. Fig. 3 compares the morphologies of SiGe and Si SEG deposited at a fixed temperature, 750°C. It appears that {111} and {311} facets appear and rapidly propagate in SiGe whereas no faceting effect is observed in silicon. Note that the appearance of {111} facets is specific to SiGe as it is never/rarely observed in silicon in this configuration. Etching facets Considering etching as a negative deposition, it is of interest to investigate possible faceting effect in chemical vapor etching. Fig. 4 gives two typical etching profiles obtained by submitted SiO2 patterned (100) wafers to an HCl/H2 mixture at 900°C. Both {111} and {311} facets are observed when using low PHCl (17 Pa), and only {311} ones with high PHCl (256 Pa). Then, we note that etching features have important similarities with epitaxy, and again kinetics is found to play a major role. Conclusion In the final paper, the kinetics of both processes (epitaxy and etching) will be given for the main high density planes. This way, we will able to explain at a certain degree most of the faceting effects observed. In addition, as a conclusive part, these results will be used as a basis to tentatively discuss and precise the physics involved in faceting.

The facets propagation during silicon and SiGe epitaxial growth has been studied in terms of morphology and kinetics. In a similar way the faceting effects during chemical etching of monocrystalline silicon have been examined. In both cases, the appearance of certain facets in certain experimental conditions have been explained on the basis of activation energies of the growth kinetics of the main high density crystal planes.

Advanced devices may today require implantation and annealing steps after the metallic interconnection realization. Depending on the application, a thin p-doped layer has to be formed after wafer bonding. The issue, in such a case, is to correctly anneal the Boron implanted layer without degrading the buried devices and interconnections which lies at a depth around 3mum below the surface. Here, the authors propose to study different way to anneal this thin p-doped layer. Low energy and low dose implantations are performed without reaching the amorphisation threshold. Long thermal annealing at 400degC (RTP) and UV laser annealing are investigated through sheet resistance, thermal wave, SIMS or TEM. On one hand, a significant activation is obtained with RTP at temperature as low as 400degC and that Boron is activated with a better activation rate with B+ than with BF2 +. On the other hand, a much better activation was achieved with laser annealing as compared to RTP regardless of the implantation conditions

In this paper, we are investigating the silicon growth on such profiles resulting from the vapour phase HCl treatment. Facet apparition and kinetics are investigated as a function of the temperature and initial surface morphology

This paper quantifies using Room Temperature Photoluminescence (PL) the substitutional carbon incorporation in SiGe epitaxial films at a function of the deposition temperature. Thanks to SIMS analysis, the better substitutional carbon incorporation at low deposition temperatures is shown to reduce the boron diffusion from SiGeC films.

In this paper, the authors presented an integration strategy for metal gate GAA transistors made by SON process using poly-gate replacement through contact hole (PRETCH). Double gate (DG) type MOSFETs, including planar DG gate-all-around and fin-FETs are today known as the best candidates for the ultimate sealing of the logic CMOS technologies on silicon. One of the main difficulties in optimizing DG devices is the control of the threshold voltage (Vth) from high performances to low power devices. With polysilicon gates, a higher channel doping has to be used when lowering the silicon thickness (TSi). This adjustment strategy has its limits and thus, gate workfunction engineering seems necessary for thin DG transistors.

In this work, we studied the effect of the deposition temperature, partial pressure and crystallite texture on the poly/epi growth rate ratio by decomposition of silane. Deposition was performed by rapid thermal chemical vapor deposition (RTCVD) in the temperature range 590<T<720°C and in the silane partial pressure range 0.14<P<1.7Torr. For monocrystalline silicon, we have observed that growth rate is proportional to the silane partial pressure. On the other hand, we have shown that for “polysilicon” the growth rate ratio slightly increases with partial pressure, like the amorphous content. For a fixed temperature, we found that amorphous content is related to the silane partial pressure and that the growth rate ratio is strongly dependent on the polycrystal roughness. It results in a non-monotonous trend of growth rate ratio versus silane partial pressure. From our experiments, we have obtained growth rate ratio varying from 1.2 to 2.5.