Analog in-memory computing (AIMC) has gained popularity as an alternative to conventional von Neumann architectures for deep learning inference, offering significant energy and latency advantages. By exploiting the analog properties of memory devices, matrix-vector multiplications can occur within memory arrays, thereby eliminating the movement of weights and associated costs. However, operating in the analog domain introduces a range of non-idealities that hamper the computational precision. These non-idealities can be stochastic or deterministic and are often difficult to characterize analytically due to their complexity and interplay with one another. In this work, we present a data-driven modeling framework that captures the behavior of AIMC hardware using experimental data from the hardware itself. Our approach is grounded in a first-order Taylor approximation of the matrix-vector multiply operation, which leads to the decomposition of the overall error into two components: linear perturbations, mainly stemming from device variability, and non-linear or recurrent residual error, typically induced by circuit-level effects and recurrent noise sources. We demonstrate that this two-model approach can faithfully reproduce the behavior of a real phase-change memory-based AIMC chip. We also show generalization to downstream inference tasks on four different networks, two ResNets for image classification and two LSTMs for character prediction and image captioning, demonstrating that the model predicts the hardware error and task performance in a diverse set of tasks.

In this work, a compact model for mushroom‐type phase‐change memory devices is introduced that incorporates the shape and size of the amorphous mark under different programming conditions, and is applicable to both projecting and non‐projecting devices. The model includes analytical equations for the amorphous and crystalline regions and uniquely features a current leakage path that injects current at the outer edge of the electrodes. The results demonstrate that accurately modeling the size and shape of the phase configurations is crucial for predicting the full‐span of the RESET and SET programming, including the characteristics of threshold switching. Additionally, the model effectively captures read‐out behaviors, including the dependence of resistance drift and bipolar current asymmetry behaviours on the phase configurations. The compact model is also provided in Verilog–A format, so it can be easily used in standard circuit‐level simulation tools.

Modern computing relies on separate components for data capture and processing. However, this often leads to computational latency and congestion in data processing infrastructures. Using device level demonstrations, in this work, we propose a phase-change computational sensor that utilizes reconfigurable load lines to perform in-sensor-in-memory computations. This is achieved through a combination of the crossbar topology of the sensor array and the non-volatile reconfigurability of conductance states in phase-change memory devices. We show that certain pre-processing computations, such as convolutional operations, can be offloaded from the in-memory processor to the sensor to create intelligent edge sensors.

Analog in-memory computing (AIMC) leverages the inherent physical characteristics of resistive memory devices to execute computational operations, notably matrix-vector multiplications (MVMs). However, executing MVMs using a single-phase reading scheme to reduce latency necessitates the simultaneous application of both positive and negative voltages across resistive memory devices. This degrades the accuracy of the computation due to the dependence of the device conductance on the voltage polarity. Here, we demonstrate the realization of a 4-quadrant MVM in a single modulation by developing analog and digital calibration procedures to mitigate the conductance polarity dependence, fully implemented on a multi-core AIMC chip based on phase-change memory. With this approach, we experimentally demonstrate accurate neural network inference and similarity search tasks using one or multiple cores of the chip, at 4 times higher MVM throughput and energy efficiency than the conventional four-phase reading scheme.

The goal of this thesis is to gain new insights into the drift phenomenon and identify strategies to mitigate it. An extensive experimental characterization of PCM devices and in particular drift forms the foundation of each chapter. With respect to time-scales, ambient temperature, device dimensions, and combinations thereof, drift is studied under unprecedented conditions. In three studies, different aspects of drift are examined. (1) The origin of structural relaxation: Drift measurements over 9 orders of magnitude in time reveal the onset of relaxation in a melt-quenched state. The data is used to appraise two models, the Gibbs relaxation model and the collective relaxation model. Additionally, a refined version of the collective relaxation model is introduced and the consequences of a limited number of structural defects are discussed. (2) Exploiting nanoscale effects in phase change memories: Scaling devices to ever-smaller dimensions is incentivized by the requirement to achieve higher storage densities and less power consumption. Eventually, confinement and interfacial effects will govern the device characteristics. Anticipating these consequences, the feasibility to use a single element, Antimony, is assessed for the first time. The power efficiency, stability against crystallization, and drift are characterized under different degrees of confinement. (3) State-dependent drift in a projected memory cell: New device concepts are aiming to reduce drift by decoupling the cell resistance from the electronic properties of the amorphous phase. A shunt resistor scaling with the amount of amorphous material is added. Simulations and the drift characteristics of a projected device put the idealized concept to the test. The contact resistance between the phase change material and the shunt resistor is identified as a decisive parameter to achieve the desired device properties.

The need to repeatedly shuttle around synaptic weight values from memory to processing units has been a key source of energy inefficiency associated with hardware implementation of artificial neural networks. Analog in-memory computing (AIMC) with spatially instantiated synaptic weights holds high promise to overcome this challenge, by performing matrix-vector multiplications (MVMs) directly within the network weights stored on a chip to execute an inference workload. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and communication to move towards configurations in which a full inference workload is realized entirely on-chip. Moreover, it is highly desirable to achieve high MVM and inference accuracy without application-wise re-tuning of the chip. Here, we present a multi-core AIMC chip designed and fabricated in 14-nm complementary metal-oxide-semiconductor (CMOS) technology with backend-integrated phase-change memory (PCM). The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks. We demonstrate near software-equivalent inference accuracy with ResNet and LSTM networks while implementing all the computations associated with the weight layers and the activation functions on-chip. The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS/W for 8-bit input/output matrix-vector multiplications.

Achieving sufficient compute precision in matrix-vector multiply (MVM) operations is a key challenge for analog in-memory computing (AIMC) that relies on resistive memory devices. A device-level concept that addresses this challenge is that of projected-type phase-change memory (Proj-PCM). Here we present Proj-PCM devices based on carbon-based projection layer (CPL). We integrated these devices onto multi-tile AIMC chips fabricated in 14nm CMOS technology. CPL is shown to exhibit superior compatibility with the phase-change material layer (PCML) as well as the BEOL process. CPL also provides sufficient tunability of resistance window. The compute tiles with CPL-based Proj-PCM are shown to achieve higher computational precision compared to those with standard PCM devices.

Accurate programming of non-volatile memory (NVM) devices in analog in-memory computing (AIMC) cores is critical to achieve high matrix-vector multiplication (MVM) accuracy during deep learning inference workloads. In this paper, we propose a novel programming approach that directly minimizes the MVM error by performing stochastic gradient descent optimization with synthetic random input data. The MVM error is significantly reduced compared to the conventional unit-cell by unit-cell iterative programming. We demonstrate that the optimal hyperparameters in our method are agnostic to the weights being programmed, enabling large-scale deployment across multiple AIMC cores without further fine tuning. It also eliminates the need for high-resolution analog to digital converters (ADCs) to decipher the small unit-cell conductance during programming. We experimentally validate this approach by demonstrating an inference accuracy increase of 1.26% on ResNet-9. The experiments were performed using phase change memory (PCM)-based AIMC cores fabricated in 14nm CMOS technology.

Analog in- memory computing (AIMC) using memristive devices is considered a promising Non-von Neumann approach for deep learning (DL) inference tasks. However, inaccuracies in the programming of devices, that are attributed to conductance variations, pose a key challenge toward achieving sufficient compute precision for DL inference. Fortunately, conduction variations in memristive devices, such as phase-change memory (PCM) devices, exhibit a strong state dependence. This state dependence can be exploited in synaptic unit cells that comprise more than one memristive device, to encode positive or negative weights. In such multi-memristive unit cells, we propose a method that optimally maps the weights to the device conductance values, by maximizing the number of devices at the stable SET and RESET states. We demonstrate that this method reduces the matrix-vector multiplication (MVM) error and is more resilient to non-ideal device retention characteristics. With this approach, we increase the mean experimental inference accuracy of a network trained for MNIST classification by 0.71% on two PCM-based AIMC cores, and the hardware-realistic simulated top-1 accuracy of a network trained for ImageNet classification by 0.28%, while significantly reducing variability across multiple experiment instances.

Non-volatile memories based on phase-change materials have gained ground for applications in analog in-memory computing. Nonetheless, non-idealities inherent to the material result in device resistance variations that impair the achievable numerical precision. Projected-type phase-change memory devices reduce these non-idealities. In a projected phase-change memory, the phase-change storage mechanism is decoupled from the information retrieval process by using projection of the phase-change material’s phase configuration onto a projection liner. It has been suggested that the interface resistance between the phase-change material and the projection liner is an important parameter that dictates the efficacy of the projection. In this work, we establish a metrology framework to assess and understand the relevant structural properties of the interfaces in thin films contained in projected memory devices. Using X-ray reflectivity, X-ray diffraction and transmission electron microscopy, we investigate the quality of the interfaces and the layers’ properties. Using demonstrator examples of Sb and Sb2Te3 phase-change materials, new deposition routes as well as stack designs are proposed to enhance the phase-change material to a projection-liner interface and the robustness of material stacks in the devices.

The precise programming of crossbar arrays of unit-cells is crucial for obtaining high matrix-vector-multiplication (MVM) accuracy in analog in-memory computing (AIMC) cores. We propose a radically different approach based on directly minimizing the MVM error using gradient descent with synthetic random input data. Our method significantly reduces the MVM error compared with conventional unit-cell by unit-cell iterative programming. It also eliminates the need for high-resolution analog-to-digital converters (ADCs) to read the small unit-cell conductance during programming. Our method improves the experimental inference accuracy of ResNet-9 implemented on two phase-change memory (PCM)-based AIMC cores by 1.26%.

Phase Change Memory (PCM) is an emerging technology exploiting the rapid and reversible phase transition of certain chalcogenides to realize nanoscale memory elements. PCM devices are being explored as non-volatile storage-class memory and as computing elements for in-memory and neuromorphic computing. It is well-known that PCM exhibits several characteristics of a memristive device. In this work, based on the essential physical attributes of PCM devices, we exploit the concept of Dynamic Route Map (DRM) to capture the complex physics underlying these devices to describe them as memristive devices defined by a state-dependent Ohm's law. The efficacy of the DRM has been proven by comparing numerical results with experimental data obtained on PCM devices.

Nanoscale resistive memory devices are being explored for neuromorphic and in-memory computing. However, non-ideal device characteristics of read noise and resistance drift pose significant challenges to the achievable computational precision. Here, it is shown that there is an additional non-ideality that can impact computational precision, namely the bias-polarity-dependent current flow. Using phase-change memory (PCM) as a model system, it is shown that this "current-voltage" non-ideality arises both from the material and geometrical properties of the devices. Further, we discuss the detrimental effects of such bipolar asymmetry on in-memory matrix-vector multiply (MVM) operations and provide a scheme to compensate for it.

In the mammalian nervous system, various synaptic plasticity rules act, either individually or synergistically, over wide-ranging timescales to enable learning and memory formation. Hence, in neuromorphic computing platforms, there is a significant need for artificial synapses that can faithfully express such multi-timescale plasticity mechanisms. Although some plasticity rules have been emulated with elaborate complementary metal oxide semiconductor and memristive circuitry, device-level hardware realizations of long-term and short-term plasticity with tunable dynamics are lacking. Here we introduce a phase-change memtransistive synapse that leverages both the non-volatility of the phase configurations and the volatility of field-effect modulation for implementing tunable plasticities. We show that these mixed-plasticity synapses can enable plasticity rules such as short-term spike-timing-dependent plasticity that helps with the modelling of dynamic environments. Further, we demonstrate the efficacy of the memtransistive synapses in realizing accelerators for Hopfield neural networks for solving combinatorial optimization problems.

Chalcogenide phase change materials enable non‐volatile, low‐latency storage‐class memory. They are also being explored for new forms of computing such as neuromorphic and in‐memory computing. A key challenge, however, is the temporal drift in the electrical resistance of the amorphous states that encode data. Drift, caused by the spontaneous structural relaxation of the newly recreated melt‐quenched amorphous phase, has consistently been observed to have a logarithmic dependence in time. Here, it is shown that this observation is valid only in a certain observable timescale. Using threshold‐switching voltage as the measured variable, based on temperature‐dependent and short timescale electrical characterization, the onset of drift is experimentally measured. This additional feature of the structural relaxation dynamics serves as a new benchmark to appraise the different classical models to explain drift.

Phase‐change memory devices have found applications in in‐memory computing where the physical attributes of these devices are exploited to compute in places without the need to shuttle data between memory and processing units. However, nonidealities such as temporal variations in the electrical resistance have a detrimental impact on the achievable computational precision. To address this, a promising approach is projecting the phase configuration of phase change material onto some stable element within the device. Here, the projection mechanism in a prominent phase‐change memory device architecture, namely mushroom‐type phase‐change memory, is investigated. Using nanoscale projected Ge2Sb2Te5 devices, the key attributes of state‐dependent resistance, drift coefficients, and phase configurations are studied, and using them how these devices fundamentally work is understood.

Can analog in-memory accelerators provide sufficient accuracy for AI applications under ambient temperature variations? Here, we answer this question by focusing on phase-change memory (PCM)-based deep learning acceleration. We investigate for the first time the impact of temperature on multi-level PCM conductance states used to store the synaptic weights. First, we characterize the temperature and drift behavior of 10,000 doped Ge2Sb2 Te5 (GST)-based mushroom PCM. Next, we present a model which can capture this behavior and faithfully reproduce the complete time-temperature dependence of the conductance states. Finally, we experimentally study the sensitivity of various network architectures to ambient temperature variations. For this, we employ a multi-layer perceptron, a convolutional neural network and a recurrent neural network, with more than 1.1M PCM weights. We demonstrate that a simple array-level scaling could correct for the conductance shift due to temperature and drift and prevent any significant accuracy drop for all the studied networks during inference.

Phase change memory (PCM) is rapidly emerging as a promising candidate for building non-von Neumann accelerators for deep neural networks (DNN) based on in-memory computing. However, conductance drift and noise are key challenges for the reliable storage of synaptic weights in such accelerators. We demonstrate, for the first time, conductance drift and noise mitigation by integrating a projection liner into multilevel mushroom-type PCM devices. While the projection liner has little effect on SET-state drift (crystalline phase), it substantially reduces drift for RESET states (amorphous phase) and improves the overall noise across SET and RESET states. Further improvement in drift is demonstrated by combining projection liner with a low-drift GeSbTe (GST) phase-change material variant. Lower drift and lower device-to-device drift variability for devices with projection liner are confirmed with large-scale experiments of over 1,000 devices. Moreover, we demonstrate using 10,000 projected PCM devices that tighter closed-loop programming distributions can be achieved, which is critical for in-memory computing based accelerators for applications such as DNN inference. Simulations show that the lower drift and device-to-device drift variability significantly increase the inference life span of PCM-based DNN accelerators.