This paper proposes an efficient and accurate method to model atomistic dopant migration, by leveraging the emerging deep neural network (DNN). By performing nudged elastic band (NEB) simulations of three prototype systems (B-doped Si, Li-doped Si, and C-doped GaN), it is shown that the proposed DNN-based method runs about 10(4)-10(5) times faster than the widely-used atomistic dopant migration modeling method based on density functional theory (DFT), meanwhile keeping DFT-level high accuracy. Active learning is used to reduce training set redundancy, and the DNN model is further optimized for more accurate NEB calculation. As a result, the dopant atomic position in saddle-point and the dopant migration energy barrier in the migration energy path (MEP) predicted by the proposed DNN-based NEB deviate merely about 10(-2) angstrom and 10(-2) eV, respectively, from those predicted by the established DFT-based NEB. Given its efficiency and accuracy, the proposed DNN-based method might be useful to develop future-generation atomic-scale technology computer-aided design (TCAD) tools.

Using a full design-technology cooptimization (DTCO) framework, we benchmark gate-all-around (GAA) nanosheet (NS) FETs against FinFETs at 3-nm logic technology relevant dimensions. First, to understand the intrinsic gain from NS, both device architectures are simulated using fixed technology ground rules [contact poly pitch (CPP), metal pitch ${M}_{x}$ , and cell height] and process assumptions (PAs), including stress, doping, junctions, and oxide thickness. Full geometry optimization along the CPP direction (gate length ${L}_{\text {G}}$ , spacer thickness ${T}_{\text {SP}}$ , and contact length ${L}_{\text {CNT}}$ ) is done to self-consistently account for tradeoff between short-channel effects (SCE), intrinsic and extrinsic resistances, and capacitances (device and parasitic). This leads to independent optimum design specifications for each Fin and NS architectures. Impact of Fin tapering and NS width and stack number are further investigated, showing additional design flexibility of GAA NS devices at scaled dimensions.

For the 3 nm technology node, horizontal gate-all-around nanosheet devices offer a non-disruptive process transition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3 nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both $V_{\min}$ and read delay even at smaller cell areas.

Using first-principles density functional theory based transport calculations, we evaluate the grain boundary reflection coefficients in Copper (Cu). We find that the grain boundary reflections can significantly enhance the metal resistivity in Cu interconnects. Later, using the Mayadas-Shatzkes model, we predict the possible enhancement of the metal resistivity due to the grain boundary scattering. These results identify the critical role of grain boundary reflection in polycrystalline Cu. Further, the implications of the grain boundary resistance for shrinking interconnect dimensions are discussed.

Resistance contribution within Ruthenium (Ru) interconnects, used in middle-of-the line and back-end-of- the line process in an integrated circuit, are evaluated using first-principles density functional theory based transport calculations using the non-equilibrium Green's function. Three prominent scattering mechanisms impurity scattering, interface/surface scattering and grain-boundary reflections are studied systematically. The results are compared with available resistivity data from literature. The calculated reflection coefficients (R) for the symmetric-tilt grain boundaries lie in the range of 0.38 to 0.51, indicating the grain boundary reflections can significantly enhance the metal resistivity within Ru interconnects. These grain boundary reflection coefficients are in good agreement with hardware data and a fit to the measured resistivity data predicts an average reflection coefficient of 0.51 for Ru interconnect, using Mayadas-Shatzkes model. The results obtained provide useful physical insights into Ru grain-boundary reflections and can be used to classify the metals for advanced interconnect technology.

Summary form only given. Rowhammer is a known security vulnerability in recent Dynamic Random Access Memory (DRAM) devices, where repeated access to an array of memory can flip the bits in the adjacent row owing to the charge leakage/ capacitive coupling. Several studies have documented the Rowhammer effect [1, 2]and Google's project zero demonstrates two working examples of a security exploit [3]. Furthermore, many published scenarios highlight that scaled DRAM below 32nm [1]is exposed to potential hacking attacks because of the Rowhammer problem [3], owing to reduced spacings in DRAM bits. Thus, it is only natural to test any new upcoming technology for a similar problem. Though the working mechanisms of DRAM and spin transfer torque magnetic random access memory (STT-RAM) are drastically different, whether the STT-RAM is also potentially vulnerable to an analogous Rowhammer effect or not is not documented or discussed in literature. While the mechanism of failure is high enough charge leakage in DRAM, the corresponding mechanism in STT-RAM may be the lowering of the thermal barrier because of the dipolar magnetic field exerted by adjacent selected bits. The lowering of the thermal barrier in turn can increase the probability of an erroneous bit flip. To ascertain whether the effect is substantial, nearest (A bit) and next nearest neighbour bits (B bit) adjacent to an unselected bit (O bit) are simulated as shown in Fig 1. The bit diameter is 55nm and the center to center bit spacing is 200 nm. The magnetic field at the O bit is simulated, when all the A and B bits have been assumed to have the magnetization pointing in the same direction. While this configuration does not necessarily conform to the conventional idea of selecting an adjacent row of bits or even both the adjacent rows (double sided hammering), it provides a scenario where the most favorable conditions for an erroneous bit flip can be evaluated in STT-RAM. Three magnetic layers are assumed in each bit separated by appropriate non-magnetic regions corresponding to the STT-RAM stack. The top most layer corresponds to the Free layer (FL) and can be flipped while the others are held fixed. While calculating the magnetic field at the O bit, the middle layer is assumed to have a magnetization opposite to the topmost and bottom layers. The other configuration in which the topmost layers is flipped and is parallel to the middle layer is known to give a smaller magnetic field. A magnetostatic calculation is done to determine the magnetic field at the site of the FL layer of the O bit. The average of the field over the entire volume of the O bit is evaluated as a function of bit spacing using magnetostatic calculations as shown in Fig 2. For the largest bit spacing of 200 nm the simulated field is only around 7 Oe while for a 100nm bit spacing it increases to 60 Oe. The analytical calculation assumes each magnetic layer in each bit to be a point. The vector sum of all of these at the location of the O bit is shown here. The discrepancy between the simulated and the analytical results increases as the bit spacing decreases. This is because of the assumption that each layer is assumed to be a point. To assess the impact of these fields, the string method is used to evaluate the energy barrier between two magnetic states corresponding to 0 or 1 stored on the O bit. Inset of Fig 2shows that for a field of 7 Oe the change in energy barrier is less than 1 kT which is not large enough to cause an appreciable change in the bit error rate. For example based on Eqn 18 of [4] the bit error rate will only double for a 1 kT change in energy barrier assuming a retention time of 10 years and a relaxation time of 1 ns. Even for a bit spacing of 150 nm the increase in the BER will be less than an order of magnitude. However for a smaller bit spacing of 100 nm the BER can go up by 3 orders of magnitude. Therefore, as it stands rowhammer effect in STT-RAM does not appear to be appreciable at the 200 nm bit spacing. However at lower bit spacings the effect might become prominent and would require additional design rules to circumvent. As in the case of DRAM different techniques might have to be adopted to mitigate the problem.

We present an ab initio study of dopant-dopant interactions in beryllium-doped InGaAs. We consider defect formation energies of various interstitial and substitutional defects and their combinations. We find that all substitutional-substitutional interactions could be neglected. On the other hand, interactions involving an interstitial defect are significant. Specially, interstitial Be is stabilized by about 0.9/1.0 eV in the presence of one/two Be-Ga substitutionals. Ga interstitial is also substantially stabilized by Be substitutionals. Two Be interstitials can form a metastable Be-Be-Ga complex with a dissociation energy of 0.26 eV/Be. Therefore, interstitial defects and defect-defect interactions should be considered in accurate models of Be-doped InGaAs. We suggest that In and Ga should be treated as separate atoms and not lumped into a single effective group III element, as has been done before. We identified dopant-centred states which indicate the presence of other charge states at finite temperatures, specifically, the presence of Be-int(+1) (as opposed to Be(int)(+2)at 0 K).

Modern computing systems require enhanced performance; however, the conventional memories such as Static Random Access Memory (SRAM) are inadequate to support this demand. This is mainly due to the fact that SRAM density cannot be increased commensurately with Complementary Metal-Oxide–Semiconductor (CMOS) transistor scaling. For example, typically the six-transistor (6T) SRAM, which has long been the workhorse of high-performance caches, requires a cell size of $120-200\mathrm {F} _{,}^{2}$ where F is the feature size [1]. On the other hand, Spin-Transfer Torque based Magnetoresistive Random-Access Memory (STT-MRAM) have emerged as universal memory technology due to its non-volatility, endurance, low operating voltages and ultrafast switching [2]. Further, they occupy much less area with 1T design comparable to DRAM with cell size of $6- 10 \mathrm {F}^{2}$ [1]. Thus, STT-MRAM is most suited for on-chip cache applications with highest possible density. One of the most important factors that determines the data retention time of STT-MRAM towards cache applications is the thermal stability of magnetization. It is known that with shrinking Magnetic Tunnel Junction (MTJ) dimensions, commensurate with CMOS scaling, the thermal stability of magnetization also decreases. This results in reduced retention times and increased bit error rates, posing significant challenges towards its application as cache memory. Hence, it is important to evaluate the thermal stability of magnetization as a function of decreasing MTJ diameter, to address their scalability and performance in advanced cache technology. In this article, we focus on perpendicular-MTJ and perform Micromagnetic simulations to evaluate the thermal stability factor at reduced MTJ diameter. Currently, the 22 nm nodes uses MTJ with 55–75 nm diameters [3]. First, we discuss the thermal energy barrier E b necessary for 7/21 days of data retention for L3-cache applications at different failure in time (FIT) rates. The requirement for the thermal energy barrier is given by: $\mathrm {E}_{b}=- ln[- ( \mathrm {t}_{0}/ \mathrm {t}_{p}) * ln(1 -$FIT$/ \mathrm {N}_{b})]$, where, FIT is failure in time, N b are no. of bits, $\mathrm {t}_{0}$ is the attempt frequency (assumed to be 1ns) and $\mathrm {t}_{p}$ is desired data retention time span (7/21 days). Figure 1 shows the calculated thermal energy barrier at different FIT's and data retention spans for various sizes of cache memories ranging between 1MB to 1GB. From this Figure, it is evident that the minimum thermal energy barrier should be greater than 20 KT for 1000 FIT's and 27 KT for 0.1 FIT's. Next, we calculate the thermal energy barrier of p-MTJ device to assess whether these demands can be satisfied with shrinking MTJ diameters. For this purpose, we use standard MTJ stack consisting of CoFeB as free layer with 0.85 nm thickness and its diameter varying between 5 – 60 nm to understand the scalability aspect. We perform E b calculations using a monodomain and domain wall assisted switching mechanism as mentioned in Ref. [2]. The thermal energy barriers are evaluated at three different values of temperature namely, $25 ^{\circ}\mathrm {C}($ room temperature), $100 ^{\circ}\mathrm {C}($ operational temperature) and $260 ^{\circ}\mathrm {C}($ solder reflow temperature). The required values, saturation magnetization (Ms), uniaxial anisotropy (Ks) and exchange constant (Aex) are used as measured in the GLOBALFOUNDRIES hardware [4]. Further, their temperature dependence is computed using Kinetic Monte Carlo simulations. The calculated thermal energy barriers, with varying MTJ diameters, are plotted in Figure 2 a). The MTJ diameters are varied between 5 – 60 nm which essentially encompasses 7, 10, 14 and 22nm CMOS technology nodes. The blue, red and green curves represent the data obtained at temperatures of 25, 100 and $260 ^{\circ}\mathrm {C}$, respectively. We observe that the lowest thermal barrier of approximately 30 KT can be achieved at 15 nm diameter for the highest solder reflow temperature. This implies that the MTJ diameter can be scaled down to 15 nm without compromising the thermal stability as required by 0.1 FIT's for 21 days. However, the energy barriers are drastically reduced below 15 nm diameter. Figure 2b) shows the switching efficiency figure of merit for p-MTJs, which is defined as the ratio of the energy barrier and switching current. Here, the critical switching current is calculated using the macrospin model described in Ref. [5]. From this plot it can be observed that the switching efficiency of MTJ saturates at smaller diameters. These diameter values, at which the switching efficiency saturates, reduces with increasing temperatures. In summary, we presented a comprehensive benchmarking of STT-MRAM for cache applications. The data shows that STT-MRAM is indeed scalable and can be integrated with advanced CMOS nodes. Our results clearly show that the thermal stability requirements for L3-cache can be met at even smaller MTJ diameters. Finally, the critical diameter at which the switching efficiency saturates is also dependent on temperature.

3D TCAD (Technology Computer Aided Design) process and device simulation is used to show that taller and thinner fins at the 14nm device node enable significant DC and RO performance gains for both nFET and pFET short channel devices through improvement in charge inversion andleakage current control. In particular, simulations identify a maximum in the DC and RO performance as a function of the Fin Ratio, defined as the top fin width (TCD) over the bottom fin width (BCD). At long channel, TCAD simulation demonstrates that mobility degradation observed in nFET hardware devices (but not in pFET devices) is due to the effect of quantum confinement in the fin.

SiGe FinFET devices have many unique device elements which differ from conventional Si FinFET devices. Here we discuss their threshold voltage sensitivity, stress profiles, long channel mobility behavior, and the presence of traps at the gate oxide interface. In order to achieve a well-performing SiGe FinFET device it is important to understand the physical nature of these elements and incorporate them in a well-calibrated TCAD deck. In this paper, we examine each element with experimental data and calibrate the TCAD deck by introducing new boundary conditions, implementing a new Dit extraction method, and adjusting the material parameters. Special consideration is given to the treatment of interface traps since the readout of the trap density with the conductance method used in experiments does not represent the actual trap distribution. Finally, we review the short channel transistor performance and provide guidelines on how to achieve a high-performing device.

The metal-semiconductor interface is fundamental to any semiconductor device and the success of advanced technology nodes critically depends upon the minimization of the contact resistance at the interface. In this paper, we calculate the electronic structure of a metal-semiconductor interface (TiGe/Ge contact) within the framework of first-principles density functional theory simulations. We report the modulation of the Schottky barrier height with respect to the different phases of TiGe metal and different crystallographic orientations of Ge substrate. We further compute the I-V characteristics of the TiGe/Ge contact with nonequilibrium Green's function formalism, using a two-terminal device configuration. The calculated transmission spectrum allows us to extract the contact resistance at the metal-semiconductor interface. Furthermore, the onset of Ohmic contact for p-doped TiGe/Ge interface is identified by studying the I-V characteristics as a function of increasing active carrier concentration.We find that a doping concentration of 1e 21 is sufficient to transform the Schottky contact into Ohmic and thereby achieve a least possible contact resistance at the interfaces. Our paper thus provides useful physical insights into the nanoscale details of the TiGe/Ge interfaces and can guide further process development to minimize the contact resistance.

A roadblock in utilizing InGaAs for scaled-down electronic devices is its anomalous dopant diffusion behavior; specifically, existing models are not able to explain available experimental data on beryllium diffusion consistently. In this paper, we propose a more comprehensive model, taking self-interstitial migration and Be interaction with Ga and In into account. Density functional theory (DFT) calculations are first used to calculate the energy parameters and charge states of possible diffusion mechanisms. Based on the DFT results, continuum modeling and kinetic Monte Carlo simulations are then performed. The model is able to reproduce experimental Be concentration profiles. Our results suggest that the Frank-Turnbull mechanism is not likely, instead, kick-out reactions are the dominant mechanism. Due to a large reaction energy difference, the Ga interstitial and the In interstitial play different roles in the kick-out reactions, contrary to what is usually assumed. The DFT calculations also suggest that the influence of As on Be diffusion may not be negligible.

We used density functional theory (DFT) to calculate TCAD parameters to describe dopant diffusion in Si, SiGe and Ge. The dopant profile simulated in TCAD with calculated parameters is in good agreement with experiment. It is demonstrated that DFT could help to get unknown TCAD parameters and provide valuable insights on the parameter relations supporting experimental data.

In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).

The 22FDX platform offered by GLOBALFOUNDRIES consists of a family of differentiated products architected to enable applications across a variety of market segments such as RF & Analog, Ultra-low Power (ULP), and Ultra-low Leakage (ULL). In order to ensure the successful development of these new products, as well as to meet the time-to-market constraints, predictive Technology Computer Aided Design (TCAD) tools have been extensively used to guide development efforts, narrow the experimental conditions and reduce the number of learning cycles. The areas of impact expanded to not only predicting device outcome from process input, but also to topics traditionally not addressed by TCAD. In this paper, we present a comprehensive TCAD that has been deployed to optimize core oxide transistors, define approaches to attain ULL targets, and simultaneously investigate the AC behavior at lower operating voltages while improving RF performance. The all-encompassing co-optimization of process, device and layout has been achieved within the same platform.

A physics based switching model for perpendicular magnetic tunnel junction (p-MTJ) device is presented by combining (a) 4×4 tunneling conductance matrix derived using non-equilibrium Green's function (NEGF) formalism and (b) 4×4 ferromagnetic conductance matrix derived using 4 component spin diffusion equation. It provides qualitative as well as quantitative agreement with switching voltages in spin torque experiments and further explains the pattern of asymmetry i.e. Vc, ap-> p < Vc, p-> ap observed in most of the switching experiments and Vc, ap-> p > Vc, p-> ap observed in our measured data. Starting at the materials and phenomena level of abstraction, our model provides a unique quantitative machinery for device engineers to model p-MTJ circuits and architectures.

A novel TCAD conductance integration method is presented to evaluate and extract the channel resistance as well as the three-dimensional (3D) parasitic resistance components in a FinFET device. It is shown that results with this method agree well with a well-known 3D analytical model and that the method accurately simulates the parasitic resistance of realistic 3D FinFETs. Furthermore, the method is shown to be an effective aid in designing FinFETs with minimized parasitic resistance. Finally, the method introduces a useful figure of merit (called by) that quantifies precisely the amount of current spreading that occurs in each region of the device. (C) 2016 Elsevier Ltd. All rights reserved.