With hybrid bonding (HB) pitch reduction, many challenges are arising. One of them is related to the reliability of HB-based interconnects and in particular their electromigration performances as electromigration (EM)-related degradation is intimately linked to the electrical current in addition to temperature and mechanical stresses. This study highlights a change in the failure modes for EM-related failures in HB-based interconnects when decreasing the interconnect pitch from 6.84 down to 1.44 µm. The weakest link moves from the BEOL levels to hybrid bonding ones but without affecting the projected performance under use conditions. Additional studies done on design aspects do not evidence any negative impact on the electro migration resistance of the HB brick.

This paper reviews the most significant qualification and reliability achievements obtained, over the last 6 years, by the scientific community for hybrid bonding-based interconnects (HB) also named Cu–Cu or Cu/SiO2 bonding. First, the definition of words qualification, robustness and reliability are given to avoid misunderstanding about the published results. Second, the five potential threats (moisture ingress, thermomechanical stresses, electromigration, Cu diffusion, dielectric breakdown) are presented. Finally, the publications of six industrials or Research and Technology Organizations are summarized and discussed. Most of the published data are related to qualification results (pass or fail). Few studies published in-depth studies, mainly on electromigration (Black’s parameters extraction and failure analysis) and copper diffusion (electrical and analytical characterizations). To conclude, once the manufacturing issues (surface preparation, alignment…) have been solved, this technology is robust and reliable at pitches > 1 μm as it reacts, roughly, like a conventional back-end of line (BEoL) interconnect.

Dye penetrant test has been used to detect non hermetic capacitive micromachined ultrasonic transducers (CMUTs). The method has proven its ability to highlight faulty CMUTs membranes among more than hundreds of CMUTs membranes. The fluorescence microscopy image highlights the defective CMUTs with a strong contrast and respecting the shape of the CMUTs, which makes it possible to design robust faulty CMUT automatic identification algorithms. Scanning electron microscopy has been performed in order to check the reliability the detection of the non-hermetic CMUTs. Observations confirmed the reliability of the method.

The paper reviews the robustness/reliability achievements and include previously published data related to the hybrid bonding module for W2W and D2W bonding techniques.

Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A study of the influence of hybrid bonding pitch shrinkage on a 3D stacked backside illuminated CMOS image sensor was performed from a process, device performance and robustness perspectives, from 8.8 μm down to 1.44 μm bonding pitches. As a result no defect related to smaller bonding pads was evidenced neither by thermal cycling nor by electromigration, thus validating fine-pitch hybrid bonding robustness and introduction for next generation image sensors.

A low cost packaging solution has been successfully implemented on RF MEMS switches. The encapsulation is made at wafer level by thin film packaging, it allows keeping very small footprint for the device and is fully compatible with wire bonding and flip chip assembly. In addition to their highly shrinked size, packaged switches excellent microwave performances and promising behaviors in terms of reliability, especially for redundancy schemes required by space applications.

This paper presents electromigration results on a hybrid bonding-based test vehicle to study the impact of bonding and passivation annealings on backend of line robustness. Black's parameters extraction leads to typical values of Cu-based interconnects. Electromigration lifetime remains the same whatever the bonding annealing conditions but a significant influence of passivation annealing is observed. Chemical analyses evidence the effect of the annealing atmosphere. A discussion is lead on the chemical species concentration at different locations of the stack and the reduction of the Time to Failure with passivation final annealing.

Electromigration experiments have been carried out on 3D interconnect structures with hybrid (Cu/SiO2) bonding architectures. The investigated test structures highlighted that the Cu/Cu interface provides better electromigration performance than a Cu/SiO2 interface. Moreover, the different Cu processes analyzed provide voiding mechanisms unchanged in comparison to the known damascene architecture.

In this paper, we present an innovative solution to successfully metallize Through Silicon Vias (TSV) with High Aspect Ratio (10:1). These structures represent a key element in the 3D mid-process integration approach. The metallization consists in depositing, respectively, a diffusion barrier and a seed layer, using two different conformal deposition techniques. The technique used for the barrier material is based on a MOCVD TiN process while the second one involves a copper electrografting method. An additional copper Physical Vapor Deposition (PVD) layer is temporarily deposited to fulfill the requested properties and finalize a viable TSV integration on double sided 300mm design architecture. Further electrical characterizations of Kelvin TSVs and daisy chains are obtained. On a first hand, a 33mOhm resistance value is measured for a single 10×100μm via structure. This measurement is consistent with the theoretical value expected for this particular TSV design. On a second hand, contact continuity of up to 754 via chain structures validates the potential viability of this integration architecture for 3D device manufacturing.

This paper presents the first complete electromigration study (EM tests, failure analyses, statistical analyses with lifetime extrapolation) for direct copper bonding interconnects. This study reveals excellent performances, comparable to BEoL interconnects. Nevertheless, the results show that it will be interesting to increase the precision of alignment to maximize the Cu-Cu interface in comparison of the Cu-SiO 2 to ensure high activation energy and at the end a high electromigration resistance.

The present methodology proposes to reduce curtaining artifacts using a plasma-FIB when milling relatively deep trenches. Finally, the methodology is very fast (< 1 h), simple to set up and can be automated. Its purpose consists in eliminating or reducing the origin of curtaining artifacts by judicious milling. This methodology can advantageously replace the rocking method presented in the literature.

Copper tin transient liquid phase bonding reliability was investigated with different setups including CuSn to Cu and CuSn to CuSn bonding. Additionally, a thermal treatment just after CuSn electrodeposition (ECD) was compared to the classical configuration. Thermal cycling test (TCT) was achieved with electrical and mechanical tests carried out before and after TCT to discriminate the setups. Before TCT, each configuration has very good electrical properties in terms of yield (>90%) and Kelvin resistance. Shear tests show good mechanical properties in all tested cases as well. However, SEM images reveal different kinds and densities of voids. Kirkendall voids are localized at the Cu/Cu3Sn interface. Smaller voids are visible at the initial bonding interface in the case of CuSn to Cu bonding. After TCT, configurations are well discriminated. CuSn to Cu configuration exhibits the worst properties: electrical yield drops at nearly 30% and shear strength loses 80% of its initial value. On the other hand, CuSn to CuSn configuration and configuration including the post ECD thermal treatment keep correct electrical yield above 80%, and has shear strength loss in the range of 30 to 50%. SEM images after TCT reveals crack localization mainly through Kirkendall voids planes either on top side or on bottom side. Hypotheses regarding these results are discussed.

This paper deals with electromigration tests on Dual Damascene TSV, a low-cost TSV process. Up- and down-stream stress configurations are investigated and we demonstrate the independence of the failure's localization with the electron flow direction. Thus, unlike the standard (single damascene) TSV process, the failure (copper depletion) location is always located inside the metal level directly below the TSV. A limited number of simple design rules may be used in order to ensure reliability requirements.

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.

4 mu m wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7 mu A/mu m on the static NMOS drain current. However, the ring oscillators response is not impacted.

Air gaps were successfully integrated in a multi level metallization interconnect stack using 65 nm design rules on 300 mm wafers. The proposed approach allows a low cost integration of localized air cavities using a sacrificial material to solve via misalignment issues. Air gap integration is shown to be mechanically robust and presents excellent electrical results with high gains on RC delays. In addition, air gaps structures tested in electromigration pass the targeted lifetime criterion. This easily scalable approach can be seriously considered either in aggressive interconnect geometries or in specific applications of existing technologies for which high electrical performance is locally required.

With the reduction of dimensions in interconnect copper lines, metal resistivity is seen to increase. This phenomenon is due to electron scattering on both sidewalls and grain boundaries. To reduce the grain boundary contribution and then resistivity, it becomes important to control microstructure. This paper focuses on the grain growth mechanism in a Damascene architecture. In this architecture, trenches are filled with copper. It is shown that the remaining copper on the top surface - the overburden - plays a key role in the final microstructure in the lines. Electrical results and observations are presented and discussed in terms of overburden grains extension inside the trenches. A method is proposed to quantify this grain extension.

An extraction method to determine the permittivity of ultra low k (ULK) dielectrics on real integrated structures is presented. It is a two-step method based on a comparison between measured and simulated capacitance. A best-estimate value of the k ULK value is first extracted with optimization software coupled to capacitance extraction software. Secondly, uncertainties on material and process parameters are considered to determine an error margin on the best-estimate extracted k value. The uncertainty on the best-estimate value is approximated by a function of the uncertainties on material and process variables. This function is calculated using a multi-linear approximation model and a numerical design of experiments. The same method is applied for the extraction of a ULK material k value (k ULK ) value and an effective k value (k eff ) but with two different simulation structures. In the simulation structure used for k eff extraction, an equivalent dielectric layer including the ULK layer, the etch-stop and capping layers is used. This method was applied to metal 1 single damascene structures. First results of extraction are presented for two different ULK dielectrics. With the estimated uncertainty used for the parameters in this work, the uncertainties obtained for the best-estimate value of k ULK and k effective are significant. Due to the linearity of the model, the method is still applicable with different values for parameters uncertainty. An analysis work will be realized to improve the parameters uncertainty estimation. Future work will also include extraction of ULK permittivity for more complex structures like double damascene structures.