Hyper-Dimensional Computing (HDC), a nanoscalable learning paradigm for low-energy predictions and lightweight models, has seen a surge in interest from the hardware accelerator community. Its statistical and distributed data representation leads to highly-efficient classifiers with inherent robustness to representation errors. A digital, 28nm CMOS chip, representing the first programmable HDC biosignal processor, achieves 25.6 nJ/pred. on a leading EMG gesture recognition dataset. Measurements confirm the high robustness of HDC: a 47% bit error-rate in the datapath by VDD overscaling leads to only 1.37% accuracy drop. This realization is the most efficient and robust EMG gesture classifier to date –its per-channel efficiency is $ 1312\times$ that of Artificial Neural Networks and 76 $\mathrm{m}\mathrm{i}\mathrm{l}\mathrm{l}\mathrm{i}\mathrm{o}\mathrm{n}\times$ that of Spiking Neural Networks.

This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator-based design methodology, which enables the integration of open-source and project-specific building blocks to develop differentiated functionality. The digital component generators use Chisel, the analog component generators use the Berkeley Analog Generator (BAG), and the physical design flow is implemented with Hammer. The chip totals 125 M gates and is implemented in a 16-nm finFET process. The vector accelerator achieves peak energy efficiency per task of 209 half-precision, 92 single-precision, and 56 double-precision GFLOPs/W for a matrix multiplication kernel at 0.55 V and 339 MHz.

Modern workloads, such as deep neural networks (DNNs), increasingly rely on dense arithmetic compute patterns that are ill-suited for general-purpose processors, leading to a rise in domain-specific compute accelerators [1]. Many of these workloads can benefit from varying precision during computation, e.g. different precisions among layers and between training and inference for DNNs has been shown to improve energy efficiency [2].

Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving their performance and utility. The FD-SOI silicon process enables integrated systems that can deliver dramatic improvements in energy efficiency through system integration. This chapter presents the Raven-3 and Raven-4 testchips, fully integrated and fully featured SoCs which achieve energy-efficient operation with low overhead. RISC-V processors allow for innovation and experimentation in the context of a free, open architecture. Integrated switched-capacitor voltage regulators can achieve high conversion efficiency when coupled with adaptive clock generators. Custom SRAM macros operate at low supply voltages, enabling wide voltage scaling. An integrated body-bias generator allows run-time tuning of threshold voltage for improved performance or reduced leakage. Taken together, these innovations showcase the possibilities of FD-SOI technology.

This paper demonstrates a signal analysis system-on-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing chain consists of generated instances of a time-interleaved analog-to-digital converter (ADC) followed by a digital tuner, a finite-impulse response (FIR) filter, a polyphase filter, and a fast Fourier transform (FFT) all connected to the five-stage, in-order RISC-V Rocket processor via an AXI4 bus. The generator-based design methodology is detailed, along with the agile design process of producing the fabricated design instance. The 5 mm x 5 mm chip is implemented in a 16-nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the application processor and accelerator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art application-specific integrated circuits (ASICs) proves that generators can produce performance-competitive designs.

This paper demonstrates a signal analysis SoC consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the core and the accelerators are instances produced by novel generators that allow for a wide range of parameter configurations and rapid design space exploration. The signal processing chain consists of generated instances of a time-interleaved ADC followed by a digital tuner, FIR filter, polyphase filter, and FFT all connected to the processor via an AXI4 bus. The 5 mm × 5 mm chip is implemented in a 16 nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the processor and accelerator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art ASICs prove that generators can produce competitive designs.

Dedicated hardware accelerators enable energy-efficient implementations of radio and imaging basebands. Multistandard, multi-mode radio basebands require an on-the-fly reconfigurable fast Fourier transform (FFT) accelerator that implements many different FFT sizes. An instance of a runtime-reconfigurable 2 n 3 m 5 k FFT accelerator was generated by a custom hardware generator to meet the requirements of common wireless standards (Wi-Fi, LTE). The accelerator is integrated with a RISC-V processor, and the measured 16nm FinFET chip runs up to 940MHz and consumes 0.46 to 22.6mW of power when running FFT benchmarks for Wi-Fi and LTE symbol lengths.

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article presents an agile hardware development methodology, which the authors adopted for 11 RISC-V microprocessor tape-outs on modern 28-nm and 45-nm CMOS processes in the past five years. The authors discuss how this approach enabled small teams to build energy-efficient, cost-effective, and industry-competitive high-performance microprocessors in a matter of months. Their agile methodology relies on rapid iterative improvement of fabricatable prototypes using hardware generators written in Chisel, a new hardware description language embedded in a modern programming language. The parameterized generators construct highly customized systems based on the free, open, and extensible RISC-V platform. The authors present a case study of one such prototype featuring a RISC-V vector microprocessor integrated with a switched-capacitor DC-DC converter alongside an adaptive clock generator in a 28-nm, fully depleted silicon-on-insulator process.

Rocket Chip is an open-source Sysem-on-Chip design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. Rocket Chip generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM). For SoC designers interested in utilizing heterogeneous specialization for added efficiency gains, Rocket Chip supports the integration of custom accelerators in the form of instruction set extensions, coprocessors, or fully independent novel cores. Rocket Chip has been taped out (manufactured) eleven times, and yielded functional silicon prototypes capable of booting Linux.

This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Raven3 Evaluation; and RISC-V Chip Building at UC Berkeley.

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

In this paper we introduce Chisel , a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis.

The wide unlicensed bandwidth of a 60GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation is beneficial for efficient transmitter and receiver implementation. Equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions based on the IEEE WPAN standard. Power consumption is minimized by using parallelized distributed arithmetic (DA). A 2mm ×2mm test chip in 65nm CMOS implements a 6-tap feedforward and 32-tap feedback equalizer that consumes 5.6mW at 2.0Gb/s throughput.

A fully digital polyphase spectrometer recently developed by the University of California Berkeley Wireless Research Center in conjunction with the Jet Propulsion Laboratory provides a low mass, power, and cost implementation of a spectrum channelizer for submillimeter spectrometers for future missions to the Inner and Outer Solar System. The digital polyphase filter bank spectrometer (PFB) offers broad bandwidth with high spectral resolution, minimal channel-to-channel overlap, and high out-of-band rejection.

An energy-efficient reconfigurable distributed-arithmetic FIR filter for multi-mode wireless communication is fabricated in 7M1P 90nm CMOS and occupies 1.5mm 2 . A 6-way parallel, 2-way time-multiplexed architecture with circuits for memory offset binary coding and memory partitioning enable input wordlength and tap configurability with 1-190MSample/s throughput and 10-130mW total power measured at 1.1V, 25°C.

Future lithography systems must produce chips with smaller feature sizes, while maintaining throughput comparable to today's optical lithography systems. This places stringent data handling requirements on the design of any direct-write maskless system. To achieve the throughput of one wafer layer per minute with a direct-write maskless lithography system, using 22 nm pixels for 45 nm technology, a data rate of 12 Tb/s is required. In our past research, we have developed a datapath architecture for direct-write lithography systems, and have shown that lossless compression plays a key role in reducing throughput requirements of such systems. Our approach integrates a low complexity hardware-based decoder with the writers, in order to decode a compressed data layer in real time on the fly. In doing so, we have developed a spectrum of lossless compression algorithms for integrated circuit rasterized layout data to provide a tradeoff between compression efficiency and hardware complexity, the most promising of which is Block Golomb Context Copy Coding (Block GC3). In this paper, we present the synthesis results of the Block GC3 decoder for both FPGA and ASIC implementations. For one Block GC3 decoder, 3233 slice flip-flops and 3086 4-input LUTs are utilized in a Xilinx Virtex II Pro 70 FPGA, which corresponds to 4% of its resources, along with 1.7 KB of internal memory. The system runs at 100 MHz clock rate, with the overall output rate of 495 Mb/s for a single decoder. The corresponding ASIC implementation results in a 0.07 mm2 design with the maximum output rate of 2.47 Gb/s. In addition to the decoder implementation results, we discuss other hardware implementation issues for the writer system data path, including on-chip input/output buffering, error propagation control, and input data stream packaging. This hardware data path implementation is independent of the writer systems or data link types, and can be integrated with arbitrary directwrite lithography systems.

A high-performance digital spectrometer backend ASIC has been designed for use with an off-the-shelf ADC frontend. The design is based on an architecture described in Simulink that has been field-tested on FPGA platforms for radio astronomy applications. The architecture maximizes the utilization of operators to nearly 100%. A test structure has been added to the design to support the detection of soft errors, since several space-borne applications may expose the circuit to high-energy particles. An in-house automated design flow was used to map the same Simulink description to a 90nm CMOS ASIC, preserving cycle-accurate and bit-accurate behavior. The chip operates with clock rates up to 390MHz, delivering a throughput of up to 1.56GS/s with 710 mW of power.