For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RT noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and after second spacers (HDD). We demonstrate that the triple junction has great potential in reducing significantly the variation of the device parameters such as drive current, off-state current, and overlap capacitance, originating from the non-uniformity of the offset spacer commonly used in CMOS devices below the 90 nm node.

This paper reports on the successful integration of truly diffusion-less (less-than-650/spl deg/C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 /spl mu/A//spl mu/m for an off-state of 10 /spl mu/A//spl mu/m at Vdd= -1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

This paper investigates the use of pulsed-RF decoupled plasma nitridation (DPN) for the growth of oxynitride gate dielectrics for 65 nm General Purpose (GP) applications. The effects of several DPN plasma parameters, base oxide thickness and post-nitridation anneal (PNA) conditions on device performance were evaluated. Significant gate leakage reduction and improved trade-off between the equivalent-oxide-thickness (EOT) and mobility, for scaled EOT, have been found in devices with oxynitrides grown from thicker base oxides and optimized DPN/PNA processing conditions. DPN oxynitrides with 1.1-1.4 nm EOT have maximum operating voltages above 0.8 V, as extrapolated for a 10-year lifetime.

A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device architectures (e.g., double-gate transistors, strained channels). We have optimized the process parameters and show that high-performance transistors can be realized, promising direct applicability of the results to future manufacturing.

A model for simulating 2D and 3D oxide shape for oxidation of non-planar silicon surfaces is presented. The model is based on an idea that the stress dependence of the reaction rate can be anisotropic with respect to the crystallographic orientation of silicon surface. It describes facet formation, observed in liner oxide at the corners of STI (Shallow Trench Isolation). It is also necessary to describe the shape of top STI corner which is critical in determining the MOSFET leakage.

The limits of scaling of planar Si MOSFET devices has been a subject of increasing interest in recent years. Consumer demand for high-performance electronic products has stimulated an ever-increasing rate of scaling of mainstream CMOS. Several results for devices with sub-50 nm gate lengths have already been reported (e.g. Timp et al., 1998; Chau et al., 2000; Wakabayashi et al., 2000) to approach the required performance values. We present here the results of study of manufacturability of sub-50 nm MOSFETs using tools routinely available for production of the 0.18 /spl mu/m CMOS generation. We show that by adapting 248 nm lithography, using nonequilibrium n-type junction formation and specially developed low-temperature processing, it is possible to manufacture devices with gate lengths as small as 15 nm. It is also confirmed that heavily pocketed devices with sub-50 nm gates show deterioration in performance.

The introduction of alternative gate dielectrics into advanced CMOS devices has quite an impact on the device performance. In this work transient analyses of this type of devices are made for the first time. The analyses are made by mixed-mode simulation of a ring oscillator. It is shown that this method allows a deeper insight into the device properties than mere static analysis. Utilizing the results, first design rules for advanced CMOS devices are extracted.

A new pixel readout prototype has been developed at CERN for high-energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5μm CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600krad–1.7 Mrad depending on the type of radiation. 10keV X-rays, 60Co gamma-rays, 6.5MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed.

Different methods to measure the unstable radical nitric oxide (NO) have been established. We are going to present a new method to measure intracellular calcium and NO simultaneously in endothelial cells. A new fluorescent dye (DAF-2) has been developed recently which binds NO resulting in an enhanced fluorescence. We loaded porcine aortic endothelial cells with Fura-2, a fluorescent dye commonly used to measure intracellular calcium, and DAF-2 simultaneously (cell permeable dyes). Using excitation wavelengths of lambda 340 nm (Fura-2) and lambda 485 nm (DAF-2) we could show that thrombin induces an intracellular calcium increase and simultaneously a NO formation in endothelial cells which could be blocked by a NO synthase inhibitor. This new method of a simultaneous measurement of intracellular calcium and NO provides the possibility to follow intracellular calcium and NO distributions online, and is sensitive enough to monitor changes of NO formed by the constitutive endothelial NO-synthase.

Heavy ion induced burnout is reported, for the first time, in different parts of a VIP. A 2D-simulation investigation allows a better understanding of this phenomenon and shows the importance of the epi-substrate junction parameters in the SEB occurrence

A 2D-simulation investigation determines the heavy ion failure mode of three different IGBT structures. The sensitivities of a N-channel IGBT, with and without n+ buffer and of a P-channel IGBT are compared in simulation.

Heavy ion induced destructive failures are reported in N-channel power IGBTs. For the first time, an experimental and 2D simulation investigation shows that latchup is involved in the triggering of the device.

This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.

For particular bias conditions, it is shown that a device can fail due to either single-event gate rupture (SEGR) or to single-event burnout (SEB). The likelihood of triggering SEGR is shown to be dependent on the ion impact position. Hardening techniques are suggested.