Junction leakage becomes more significant as metal-oxide-semiconductor (MOS) technologies scale down in bulk-silicon. In this work we quantify the four key elements to junction leakage generation through a combination of experiment and device simulation. These elements are: (i) ultra-shallow junction steepness, (ii) channel and pocket concentrations, (iii) junction curvature, and (iv) the presence of residual defects. We first characterize n+/p and p+/n diodes to quantify how changes in doping profiles affect reverse bias leakage. Diodes with end-of-range (EOR) silicon defects intentionally located in the junction depletion region are also characterized to quantify their contribution. This feeds into a device simulation study to gain insight in the experimental results and in the capabilities of available physical models. Thereafter simulation is used to predict leakage in future generation bulk-silicon MOS devices. In summary, band-to-band tunneling (BBT) due to aggressively scaled doping profiles and trap-assisted tunneling (TAT) due to the increased presence of defects make off-state low-standby-power leakage targets difficult to meet. With the increase of junction leakage from aggressively scaled ultra-shallow junctions, the assumption that the subthreshold leakage component dominates off-state current is no longer valid.

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La2O3, Dy2O3 and Al2O3 on both HfSiO(N) and SiO2 to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

In this work, we studied molybdenum (Mo) and its conductive oxides (MoOx) for p-type metal gate application. Three compositions of MoOx have been investigated in this work. The resistivity of Mo/MoOx was found to significantly increase with increasing oxygen incorporation. Clear phase separation of all MoOx was observed after high temperature thermal treatment. Incorporation of oxygen was found to be effective to increase the work function (WF) of Mo. However, after full integration process, significant WF decrease of MoOx was also observed, which may be induced during the high temperature junction activation process. The interfacial silicon oxide layer growth and the EOT dependent Vfb roll-off behavior will also be discussed.

In this work we demonstrate that effective tailoring of the extension junction in MOS devices with C co-implantation must be accompanied by re-optimization of the deep HDD (HDD+) profile and spacer dimensions. In this way junction and doping profile optimization can successfully improve short channel effect (SCE) control, without penalty in performance or junction leakage.

We demonstrate for the first time the CMOS integration combining inserted metal with FUSI using a novel process flow. The proposed flow allows for a flexible gate electrode and dielectric choice for island PMOSFETS, without adding excessive process complexity or additional masks. It is considered as a promising alternative for dual metal integration for 45 nm bulk CMOS technology and beyond.

In this work we investigate the effect of nitridation on HfSiO's degradation under positive constant voltage stress. A comparison between decoupled plasma nitridation, annealing in NH"3 and no nitridation is made. Stress induced leakage current dominates a wear-out phase before the final hard breakdown, regardless of nitridation. However, this progressive breakdown phase is more pronounced in NH"3 annealed samples resulting in 60 times gate current increase after 10 years, 3 times higher compared to decoupled plasma nitridation and no nitridation. On the other hand, a shorter wear out phase is responsible for faster breakdown in plasma nitrided samples.

MoON has been reported to be a good PMOS candidate. In this paper, we report tuning of the MoON PMOS metal towards Si conduction band-edge with V-T as low as 0.35V for SiON capped with DyO, using a standard high temperature gate first process flow. Consistent shifts of 450mV in V-FB and V-T are observed by capping SiON with DyO for MoON gate. Gate leakage as low as 10(-7) A/cm(2) at 17.6 angstrom EOT is obtained, outperforming HfSiON by 3 orders of magnitude. Intermixing of SiON and DyO is shown to be the key element leading to low EOT and low gate leakage without any degradation of the gate oxide integrity.

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoOxNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices

The electrical properties of La2Hf2O7 (LHO) and HfO2 (HO) high-k dielectric layers deposited by molecular-beam epitaxy are reported. Capacitors and transistors with LHO and HO gate dielectric layers and TaN metal gate electrodes deposited using physical vapor deposition were fabricated. The (SiO2) equivalent oxide thickness (EOT), the electrical oxide thickness in inversion toxinv, and the gate leakage current density (Jg) were determined on large area metal-oxide-semiconductor capacitors and metal-oxide-semiconductor field-effect transistors. HO layers with a physical thickness tph=30Å showed an EOT (toxinv) of 15.1Å (19.3Å) with Jg=8.1×10−6A∕cm2 at Vg=Vfb−1V. LHO layers deposited on SiON showed a minimum EOT (toxinv) of 18.7Å (25Å) with Jg=4×10−8A∕cm2 at Vg=Vfb−1V. The (effective) electron mobility at high E field for LHO layers was observed for a 40-Å-thick LHO layer deposited on Si with μeff=147cm2∕Vs at E=1MV∕cm. For a 30-Å-thick HO layer at identical field, μeff=170cm2∕Vs was found. LHO layers deposited on SiON interface exhibited 5%–10% higher electron mobility at high E field than identical layers deposited on Si. Further, both low E field and high E field mobilities decreased for thicker high-k layers, indicating remote charge scattering from both the interface and the bulk of the high-k dielectric. It was observed that LHO layers showed strongly reduced electron trapping in preexisting bulk defects as compared to HO layers. At E=1MV∕cm (corresponding to Vg=VT+0.6V), the trapped charges per area Ntr were Ntr<5×1010∕cm2 for the LHO layers and Ntr>5×1011∕cm2 for the HO layers. These results show that low-leakage Hf-based gate dielectric layers with low defect density can be obtained by alloying with La.

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated