Performance and negative-bias temperature instability (NBTI) on atomic-layer-deposited HfSiON metal-gated pMOSFETs are investigated. The impact of nitrogen incorporation either with plasma nitridation or NH3 anneal is studied and compared to the nonnitrided stacks. The capacitance equivalent thickness reduction that is observed in nitrided stacks is compensated by the slight decrease of the hole mobility for the same gate overdrive, resulting in no improvement of the performance. On the other hand, it is shown that nitridation strongly enhances NBTIs in these devices. Based on these results, the necessity of nitrogen incorporation in thin HfSiON/metal gate stacks should be reconsidered.

Atomic layer deposition of Hf–Si–O and using , , and was studied. The growth per cycle and composition of Hf–Si–O films were analyzed as a function of the growth temperature, the pulse sequence, and the precursor doses. The growth of Hf–Si–O from appeared to be determined not only by the –OH density but also by the –OH bonding mode. The chemistry results in carbon-free films with low chlorine impurity content. The Hf–Si–O films of Hf-rich composition are meeting the leakage-current requirements for technology node and below.

For the first time MOSFET transistor performance featuring dielectric Lanthanum Hafnium Oxide (LHO) deposited by molecular beam epitaxy are presented. These dielectrics were deposited on a SiO2-like surface and integrated into a conventional etched-gate flow featuring TaN as gate electrode. The results for reference HfO2 deposited in the same MBE tool are comparable to standard (atomic layer deposited) HfO2 in the same process flow. Long-channel LHO devices exhibit reasonably good performance, while short-channel devices are sensitive to some process issues. LHO devices exhibit excellent leakage and minimal V-t-instability compared to HfO2.

A systematic study about the flatband voltage (V-fb) shift of Ru gated metal-oxide-semiconductor stacks after thermal treatment in O-2 has been performed. The dependence of the V-fb shift on the anneal time and temperature and the thickness of Ru was studied in detail, and a clear link between the V-fb shift and an oxygen diffusion process in Ru was observed. A high temperature thermal treatment of the devices prior to the O-2 anneal has no significant impact on the V-fb shift. The V-fb shift is ascribed to the shift of metal gates' work function, and is not intrinsic to HfO2 gated stacks as similar behavior was also observed on SiO2, from the combination of internal photoemission and conventional capacitance-voltage measurement. No similar V-fb shift was observed for TiN gated stacks and the V-fb shift seems to be more related to the properties of gate electrodes other than those of gate dielectrics. After thermal treatment in O-18(2), from time-of-flight secondary ion mass spectrometry measurement, it was found that O-18 penetrated through Ru and was incorporated at around the Ru/dielectric interface, which corresponded to the formation of an interfacial RuOx layer. The thin interfacial RuOx layer was found to have very similar properties as the ones of bulk RuO2 and the mechanism of its formation was discussed from thermodynamics and kinetics points of view. We believe that the formation of a thin RuOx layer at around the Ru/dielectric interface in O-2 ambient is responsible for the increase of the V-fb for Ru gated stacks. (c) 2007 American Institute of Physics.

A systematic study of the flat-band voltage (Vfb) shift of Ru gated metal-oxide-semiconductor (MOS) capacitors subjected to thermal treatment in O2 has been performed. The dependence of the Vfb shift on the thickness of Ru, anneal temperature and time is studied. The Vfb shift is ascribed to the shift of metal gates’ work function (WF), and is not significantly dependent on the type of dielectric (HfO2 or SiO2). From time-of-flight secondary ion mass spectrometry (TOF-SIMS) measurement, it was found that after thermal treatment in 18O2, 18O penetrated through Ru and was incorporated in the Ru/dielectric interface region. We believe that the formation of the thin interfacial RuOx layer is responsible for the Vfb shift.

The nitridation effects on low-frequency (1/f) noise in metallorganic chemical vapor deposited HfO2 n- and p-metal oxide semiconductor field effect transistors (MOSFETs) are reported. Devices with a postdeposition anneal (PDA), performed after HfO2 deposition, in a N-2 or NH3 ambient were investigated. A significant variation in noise was observed when different PDAs were employed. Devices annealed with N-2 showed lower input referred noise S-VG (similar to 125 mu V-2/Hz) for parallel to V-G-V-T parallel to similar to 0.1 V, close to the ITRS specifications when compared to NH3 anneals (similar to 1100 mu V-2/Hz). Carrier trapping is shown to be the origin of the 1/f fluctuations for most n-MOSFET process splits. For p-MOSFETs, no significant impact of the PDA was observed, yielding a constant S-VG (similar to 200 mu V-2/Hz). Additionally, two types of interfacial layers were considered for n-MOSFETs, i.e., nitrided and non-nitrided interfaces, prepared by a decoupled plasma nitridation before HfO2 deposition. Different trap density profiles were derived from the noise spectra for the nitrided- and non-nitrided-interface n-MOSFETs. This suggests that nitridation can induce nitrogen-related defects which lead to a variation in the concentration of oxygen vacancies in the bulk HfO2. The binding configuration between the atoms may also play an important role.

Growing nanometer-thin HfO2 films by atomic layer deposition (ALD) for implementation in advanced transistor structures is controlled by the density of reactive OH sites on the surface. The impact of thin SiO2 starting surfaces, grown by wet chemical processes and by wetting a thermal oxide, on the nucleation and growth of ALD HfO2 has therefore been evaluated. Our results demonstrate that both surface pretreatments display the same dependence of the initial HfO2 growth on the interfacial layer thickness. This correlation is first characterized by a linear increase, which can be interpreted in terms of increasing OH surface concentration. Once an ellipsometric oxide thickness of approximately 0.8 nm is reached, saturation of the HfO2 deposition occurs. Maximal OH coverage of the surface or steric hindrance of the adsorbed precursor molecules could explain this observation. However, the increased growth-per-cycle at lower deposition temperatures can be attributed to an improved hydroxylation of the surface, excluding steric hindrance as the primary factor causing saturation. Furthermore, electrical characterization revealed that both interfacial oxides show identical leakage scaling behavior down to an equivalent oxide thickness of 0.8 nm.

The correlation between the stoichiometry of Hf-SiON gate dielectrics and mixed-signal properties of low-power MOSFETs is investigated. MOSFETs with gate length L down to 100 nm were fabricated in a conventional fabrication flow with a thermal budget of 1000 degrees C. The equivalent oxide thickness values of the gate stacks ranged from 12.0 to 14.4 angstrom. The inversion thickness t(ox)(inv) ranged between 16.2 and 18.9 angstrom. Accumulation leakage current density at V-g = V-fb -1 V ranged from 3.1 X 10(-3) to 3.9 x 10(-2) A center dot cm(-2), corresponding to a leakage reduction of around 1000 times compared with that of SiON/TaN. The inversion leakage current density at V-g = V-t + 0.7 V was found to be between 0.18 and 0.66 A center dot cm(2), i.e., 20 times lower than that of SiON/TaN. The threshold voltage instability (Delta V-t) of the high-k gate stacks was found to be below 10 mV, corresponding to a (bulk) oxide trap density N-ot < 3 X 10(10) cm(-2). Normalized input-referred gate noise spectra S,, showed minor dependence on the Hf content of the gate dielectric. This is attributed to the fact that the main sources for the low-frequency (LF) 1/f noise are defects located at the interfaces rather than bulk defects in the gate dielectric. Moderate high-and low-field mobilities of 50%-70% of a SiON/TaN reference device were found in MOSFETs with Hf-based gate dielectric. Of the investigated layers, stoichiometric (55% Hf) and Hf-rich (70% Hf) silicates on SiO2 interface show the best compromise in terms of gate leakage reduction, threshold voltage instability, LF noise, drive current, and analog voltage gain. For an HiSiON silicate dielectric layer with 70% Hf and SiO2 interface, a low-field peak electron mobility mu(eff) = 148 cm(2)/V center dot s, an oxide trap density N-ot < 1.4 x 10(10) cm(-2), and a drive current I-ON = 459 mu A/mu m at I-OFF = 9 pA/mu m were found. The analog voltage gain A(nu) of a MOSFET with this gate dielectric and W/L = 1/0.45 was found to be A(nu) = 121. To meet specifications for mixed-signal properties, optimization of dopant engineering along with tuning of the gate stack properties is required to improve the performance of high-k-based MOSFETs.

The electrical properties of La2Hf2O7 (LHO) and HfO2 (HO) high-k dielectric layers deposited by molecular-beam epitaxy are reported. Capacitors and transistors with LHO and HO gate dielectric layers and TaN metal gate electrodes deposited using physical vapor deposition were fabricated. The (SiO2) equivalent oxide thickness (EOT), the electrical oxide thickness in inversion toxinv, and the gate leakage current density (Jg) were determined on large area metal-oxide-semiconductor capacitors and metal-oxide-semiconductor field-effect transistors. HO layers with a physical thickness tph=30Å showed an EOT (toxinv) of 15.1Å (19.3Å) with Jg=8.1×10−6A∕cm2 at Vg=Vfb−1V. LHO layers deposited on SiON showed a minimum EOT (toxinv) of 18.7Å (25Å) with Jg=4×10−8A∕cm2 at Vg=Vfb−1V. The (effective) electron mobility at high E field for LHO layers was observed for a 40-Å-thick LHO layer deposited on Si with μeff=147cm2∕Vs at E=1MV∕cm. For a 30-Å-thick HO layer at identical field, μeff=170cm2∕Vs was found. LHO layers deposited on SiON interface exhibited 5%–10% higher electron mobility at high E field than identical layers deposited on Si. Further, both low E field and high E field mobilities decreased for thicker high-k layers, indicating remote charge scattering from both the interface and the bulk of the high-k dielectric. It was observed that LHO layers showed strongly reduced electron trapping in preexisting bulk defects as compared to HO layers. At E=1MV∕cm (corresponding to Vg=VT+0.6V), the trapped charges per area Ntr were Ntr<5×1010∕cm2 for the LHO layers and Ntr>5×1011∕cm2 for the HO layers. These results show that low-leakage Hf-based gate dielectric layers with low defect density can be obtained by alloying with La.

Bi-layer gate stacks consisting of a HfO/sub 2/ and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400/spl deg/C due to radical oxygens, leading to an improvement in the quality of HfO/sub 2/ with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO/sub 2/-like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO/sub 2/-like interface demonstrate RPO as a promising way for gate-stack optimization.

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed VT/Vfb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the VT-shift problem jeopardizes initial high-κ integration with poly-Si for the 65nm and also for the 45nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining VT-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.

In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 10(10) at/cm(2).

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

Direct-etched HfO2/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO2/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO2 based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal gm the leakage is lower for HfO2 based transistors, despite the lower EOT for the HfO2 based devices.

NMOS and PMOS triple gate FETs with a single mid-gap TaN gate electrode have been fabricated. This work demonstrates for the first time triple gate transistors with a high-k gate dielectric and metal gate electrode that gives more than 3 orders of magnitude lower gate leakage at comparable performance to an oxynitride-metal gate stack. A gate etch capable of removing the TaN electrode on the vertical sidewalls and underneath the active fins is demonstrated. Transistors with fin widths of 50nm yield symmetric threshold voltages in the range of 0.35V to 0.55V demonstrating that a single mid-gap metal is compatible with advanced multiple gate FET architectures. The devices with HfO2-TaN gate stack exhibit a very low gate current density of 9 x 10(-3) A/cm(2) at Tox-inv = 2.1 nm.