7nm HZO-based 2D ferroelectric capacitors $(\mathrm{C}_{2\mathrm{D}})$ down to $0.0028\mu \mathrm{m}^{2}$ area were successfully integrated in the BEOL of 22nm FDSOI node, with $2.\text{Pr} > 10\mu \mathrm{C}/\text{cm}^{2}$ and extrapolated breakdown-limited endurance $> 10^{13}$ cycles. $\mathrm{C}_{2\mathrm{D}}$ exhibit a strong layout-dependent remanent polarization that is consistent with biaxial stress reduction. $16\text{kbit}\ 1\mathrm{T}-1\mathrm{C}_{2\mathrm{D}}$ FeRAM arrays were designed and fabricated to quantitatively assess the memory window (MW) dependence with capacitor and transistor dimensions as well as operating voltages. 0 bitfail up to $10^{10}$ cycles is demonstrated on these 22nm FeRAM arrays at 2.4V, with median MW larger than 100mV. In order to reduce FeRAM bitcell footprint, 3D-based FeCap $(\mathrm{C}_{3\mathrm{D}})$ are also demonstrated, leading to 2.Pr up to $140\mu \mathrm{C}/\text{cm}^{2}$ (normalization by footprint) with projected median MW at array level of 600mV at 1.5V for $0.047\mu \mathrm{m}^{2}\ 1\mathrm{T}-1\mathrm{C}_{3\mathrm{D}}$ bitcell.

Atom probe tomography was employed to observe and derive the composition of carbon clusters in implanted silicon. This value, which is of interest to the microelectronic industry when considering ion implantation defects, was estimated not to exceed 2 at%. This measurement has been done by fitting the distribution of first nearest neighbor distances between monoatomic carbon ions (C+ and C2+). Carbon quantification has been considerably improved through the detection of molecular ions, using lower electric field conditions as well as equal proportions of 12C and 13C. In these conditions and using another quantification method, we have shown that the carbon content in clusters approaches 50 at%. This result very likely indicates that clusters are nuclei of the SiC phase.

Carbon has been co-implanted to phosphorus at low temperature (−100 °C) in silicon. As compared to a room temperature carbon implant, phosphorus activation is increased due to the suppression of extended defects. The unusual carbon depleted region observed in both secondary ion mass spectroscopy and atom probe tomography annealed profiles has been explained and modeled using an interstitialcy diffusion barrier of 0.6 eV. Carbon clusters have been interpreted as being composed of several immobile dimers carbon/self-interstitial, in agreement with the stoichiometry of the SiC phase. From the model presented here, an adequate temperature window (>750 °C) has been found regarding self-interstitials trapping by carbon.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

Atom Probe Tomography (APT) was used to quantify carbon in implanted silicon at two various electric fields (similar to 15 and 20 V/nm). Using equal proportions of implanted C-12 and C-13, the numerous molecular ions that were observed were identified and their contribution to the carbon content statistically derived. Much more accurate carbon quantification was obtained in the lowest electric field analysis by comparing APT with Secondary Ion Mass Spectroscopy profiles. This was assigned to a lower amount of molecular ion dissociations. Furthermore, the number of self-interstitials trapped per carbon atom in clusters was derived. This value of interest for the microelectronics industry regarding dopant diffusion and implantation induced defects was estimated close to one, in agreement with the expected stoichiometry of the SiC phase present in the phase diagram. However, this was obtained only when using low electric field conditions.

Dopant diffusion and structural defects are investigated in a carbon-phosphorus implanted silicon. End-of-range defects maturation and phosphorus diffusion are inhibited. A direct imaging of carbon segregation to dislocation loops is given by atom probe tomography. Segregation energies of carbon atoms to these defects are estimated to be about 0.37 eV. The comparison between observed and derived cluster radii indicates a quick decrease in the self-interstitial supersaturation during the nucleation step of carbon precipitation. Carbon clusters are likely to be the precursors of a metastable phase, which is not the expected SiC phase.

Until the 90-nm node, CoSi 2 silicide have been widely used in semiconductor industry. More recently, in order to meet performance requirements in advanced digital nodes, process integration have consensually shifted towards NiPt-based silicides [1] . Nevertheless, advanced memory and imaging technologies being still based on 90-nm core MOS, developments and studies on CoSi 2 silicide are still of the best interest as new challenges are emerging.

In this work, heated implantation impact on defect generation is observed for non-amorphizing conditions and specific anneal. Photoluminescence imaging method has been used and exhibits radiative defect density variation with chuck temperature. Moreover, to understand the behavior of such implantation in terms of defect generation and depth profile, effectiveness of Kinetic Monte Carlo (KMC) simulations is discussed.

To co-integrate bipolar devices with 28 nm FDSOI CMOS using the epitaxial extrinsic base isolated from the collector architecture, an epitaxy is needed on a pre-implanted SOI. The issue of thin film agglomeration induced by epitaxy pre-bake is addressed. Particularly, it is shown that high dose implantation induced damages and point defects lead to a decrease of the SOI critical temperature of agglomeration. In this study, heated implantation is proposed in order to solve this issue.

The impact of the amorphous silicon (a-Si) thickness generated by the Pre-Amorphization Implantation (PAI) process and the potential benefits of adding a carbon implantation step on the Ni-silicidation process was evaluated. The silicide resistivity is improved in the same way when Si or Ge PAI process is performed compared to the reference sample. However, the specie used for PAI has an impact on the silicide roughness. Adding carbon after Ge or Si implantation reduces the silicide roughness at the expense of an increased resistivity. It has also a positive impact on the Pt distribution in the silicide and its thermal stability.

This paper deals with the optimization of a Si/SiGe HBT featuring an implanted collector and a DPSA-SEG emitter-base architecture. Arsenic and phosphorous doping species are studied. On the one hand, both silicon defects and dopants profiles control are evaluated and on the other hand, hf performances are presented. Carbon-phosphorous co-implantation is also investigated and a state-of-the-art 450 GHz fT HBT compatible with 55-nm MOSFETs is demonstrated through a device layout study.

In this paper, in order to provide a comprehensive overview of the opportunities and limitations of the metal/insulator/semiconductor contacts approach, expected performance based on ideal contact simulations as well as key practical aspects are presented. While the former give us a glimpse of the theoretical potential of this paradigm, mainly to contact nFETs, the latter highlights concerns about the electrical characterization of such contacts along with issues occurring during their physical implementation.

Alors que nous approchons des nœuds technologiques ultimes dans le domaine de la logique numerique, la reduction de leurs dimensions est d’avantage impactee sur la longueur de leurs contacts plutot que sur leur grille. Des lors, il apparait necessaire de reduire significativement la resistivite de ces contacts afin de ne pas degrader les performances des futurs nœuds technologiques.Cependant, a cause de l’ancrage du niveau de Fermi, la plupart des metaux utilises dans la micro-electronique presentent un travail de sortie effectif tres eloigne de sa valeur theorique lorsque mis en contact avec du silicium. Prevenant toute modification de la hauteur de barriere Schottky a l’interface, ce phenomene empeche l’optimisation de la resistivite de contact. Afin de l’endiguer, une approche recente consiste a inserer une couche de dielectrique au sein du contact formant ainsi une jonction Metal/Isolant/Semi-conducteur (MIS). Neanmoins, la plupart des etudes presentees dans l’etat de l’art ont ete realisees dans des environnements non-industriels, visant d’avantage a l’obtention de preuves de concept plutot qu’a l’integration de contacts MIS dans des produits manufactures.Ce travail de these consiste donc a i) analyser le schema optimal d’integration de contacts MIS simultanement sur substrats n et p presentant des concentrations de dopants relativement elevees ; ii) Evaluer l’impact de tels contacts sur les performances des nœuds avances ; iii) Fabriquer des contacts MIS dans un environnement semi-industriel en utilisant les materiaux conventionnement utilises en micro-electronique avancee ; iv) Evaluer les proprietes effectives des contacts MIS ainsi fabriques.

We present experimental and simulated J-V characteristics of Metal/Insulator/Semiconductor (MIS) junctions aiming at improving the contact resistivity for advanced CMOS nodes. We show that an Atomic Layer Deposition (ALD)-based Al 2 O 3 process may induce a native silicon oxide regrowth leading to an additional tunneling resistance in series. A modelling-based analysis of Metal/Insulator/Insulator/Metal (MIIS) contacts, including the potentially beneficial interfacial dipole, provides a new outlook on high-κ/SiO 2 bilayers for low resistivity contacts.

We demonstrate in this paper a fast and simple method for evidencing and classifying the ambipolar response of tunneling-based field effect transistors in pull-down (nFET-like) and pull-up (pFET-like) modes. This technique enables to unequivocally determine whether carrier injection on either side of the device occurs via band-to-band-tunneling or single carrier tunneling through a Schottky barrier. It was applied to Silicon On Insulator (SOI) and SiGeOI tunnel FETs, which were fabricated to be nominally identical, yet showed a discrepancy of several orders of magnitude in ON-state current. The electrostatic analysis of their respective ambipolar signature revealed that the high-drive-current devices were in fact operating like Schottky barrier FETs in the pull-up mode due to a silicidation defect occurring only on the n-doped side. These new findings bring about a reassessment of previously published results in terms of on current-subthreshold swing tradeoff perspectives for nanowire SiGe pTFETs. On the other hand, the resulting unintended asymmetrical device geometry suggests a possible route to fabricating Schottky barrier FETs with reduced parasitic leakage.

Aiming at overcoming the Fermi-level pinning (FLP) occurring at the metal/semiconductor interfaces, metal/insulator/semiconductor (MIS) contacts to n-Si and p-Si are usually treated in separate optimization studies, yet with no particular insight on their technological compatibility. In this paper, using 1-D analytical modeling of MIS contacts, it is shown that in order to fully benefit from FLP mitigation on both n- and p-type Si, a single-insertion/single-metallization scheme cannot be considered. In addition, it is demonstrated that associating given numerical values of contact resistivity with MIS contacts results in a thorny problem, since their I-V characteristics are nonsymmetric nonlinear.

In this paper, some key fundamental aspects of Metal / Insulator / Semiconductor contacts as well as practical issues occurring with their implementation are reviewed in order to fully comprehend the opportunities and limitations of this approach.