RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{ON}}\times C_{\text{OFF}}$</tex> of 78 fs with a breakdown voltage of 3.7 V.

Flexibility on the gate-to-drain/source overlap length is useful for selecting the best compromise between device performance (including short channel effects and gate scaling, ON-state current, parasitic overlap capacitance), and the device reliability to hot-carrier degradation. In this paper, the performance and reliability of transistors with variable overlap is studied in a 40 nm CMOS technology. A double-hump is observed in the substrate current characteristic in function of the gate voltage for low-overlap transistors. An analysis of the origin of the second substrate current hump is conducted, and it is attributed to impact ionization at the drain-side, source-side or both depending on the overlap. TCAD simulations are performed to explain the two possible origins of the double-hump characteristic, which are degradation of the gate control over the channel due to low overlap or hot-carrier trapping. Finally, electrical characterizations are conducted to measure the degradation rate for various overlap lengths. It is observed that a longer overlap gives the transistor a longer lifetime under hot-carrier stress conditions.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.

A new transistor architecture is developed by reusing already existing fabrication process bricks in an embedded non-volatile memory (eNVM) sub-40 nm CMOS technology, resulting in a middle-voltage zero-cost transistor, ideal for low-cost products. TCAD simulations are undertaken to confirm the feasibility of the process optimization and predict the transistor performance and reliability. The new transistor is fabricated then electrically characterized. The new device shows good analogue performances for no cost added. A hot-carrier injection (HCI) degradation evaluation is performed and confirms the reliability of the device.

This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transistors used in analog and digital applications is 5% higher due to the reduction in the STI-induced, compressive stress in the channel. The polysilicon wall could be added automatically in digital standard cells during cad to mask operation without increasing the size of the cells. Finally, the speed frequency of CMOS inverter ring oscillators designed with low-voltage MOSFETs used in digital standard cells is increased by 6% when a polysilicon wall is added around NMOS transistors. Moreover, the static current of ring oscillators remains unchanged.

In this paper, carrier effective mobility is accurately extracted from weak to strong inversion and from ohmic to saturation regimes by pairing the split C-V technique with charge-sheet model. In weak inversion, both electron and hole effective mobility are found to be constant and V-DS independent. Moreover, effective mobility extracted by this new method is modeled in all regimes using already published models extended up to the saturation regime. (C) 2015 Elsevier Ltd. All rights reserved.

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.

This paper presents several layout optimizations in order to decrease both, the internal power and the area of digital standard cells. A new D flip-flop (Dff) is designed using advanced design rules and lower active widths. Post-layout simulations are performed and the internal power of a new Dff is reduced by 20% while clock-to-Q delay remains unchanged. Indeed, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. The saturation current (IDSAT) is improved by 15% and 50% for NMOS and PMOS transistors, respectively. Moreover, the area of the new Dff is reduced by 20% by using lower active widths and new optimized design rules.

To improve analogue circuit reliability, the evolution of VT and VT matching under hot carrier injection (HCI) stress has been investigated on standard and octagonal MOSFETs. An important degradation can be observed on standard devices due to the presence of parasitic corner transistors. The specific structure of octagonal MOSFETs removes parasitic transistors and reduces VT degradation. Moreover, the residual VT degradation of octagonal MOSFETs, which is asymmetric, is further reduced by reversing source and drain connections.

Low power analog applications are often designed under threshold and can be degraded by hump effect. This effect is explained through device dimensions and body bias studies. A MOSFET matching improvement in sub-threshold area is demonstrated with active “multi-fingers” test structure.

Analog circuit designs are often biased to work in sub-threshold mode for low power constraints and for better gate-source voltage matching performances. Depending on process, hump effect may change MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. Actually, even without body effect, hump mainly degrades MOS matching performances in the sub-threshold area with significant temperature dependence. Thus, in order to accurately simulate bandgap performances, modeling of hump effect has to be considered.

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, VT shift due to Hot Carrier Injection stress is accelerated on small width devices. VT matching is also degraded during stress as a function of VT deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.