In this work, radio-frequency and traps properties of unintentionally doped polycrystalline silicon (polySi) deposited by low pressure chemical vapor deposition (LPCVD) on high resistivity silicon (HR-Si) substrate are characterized. Both volume (i.e. inside polySi) and interface traps (i.e. near polySi/HR-Si) are detected by photo-induced current transient spectroscopy (PICTS). A thermal budget of 900 degrees C during 2 h is sufficient to observe trap densities reduction near the polySi/HR-Si interface, affecting the RF performance of the fabricated substrates.

The design of RadioFrequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT)-based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

This study investigates the impact of back-gate bias-induced interfaces on the zero-temperature-coefficient (ZTC) point in fully depleted SOI transistors, revealing its fundamental mechanism through mutual compensation between threshold voltage (Vth) shifts and interface-affected carrier mobility. Experimental results demonstrate that the ZTC point systematically tracks Vth modulation and interface effects with varying Vgb. Notably, positive Vgb significantly narrows the gap between ZTC and Vth, as the dominant conduction channel shifts toward the high-quality bottom interface with minimal interface states influence.

Cryogenic CMOS circuits are gaining interest due to the emerging of quantum computing. FDSOI MOSFETs are ideal for low-power circuits at cryogenic temperatures, offering threshold voltage tunability. However, thermal effects can hinder performance gains. The low thermal conductivity of some materials causes local temperature increases, affecting electrical performance. This work addresses self-heating in 28nm FDSOI transistors down to 4K, presenting experimental results on thermal resistance, spatial and temporal extension of thermal effects, discussing their impact on performance and reliability.

In this study, radiation-induced degradation, which is caused by total ionizing dose (TID) and displacement defect (DD) effect, is investigated in fully depleted silicon-on-insulator (FD SOI) nanowire field-effect transistors (NWFETs) under 25-MeV proton irradiation. The combined effect of TID and DD degraded the subthreshold swing (SS) and OFF-state current (Ioff) of n-type FD SOI NWFETs, while it degraded the threshold voltage (Vth) and ON-state current (Ion) of p-type FD SOI NWFETs. This degradation was sensitive to increases in proton fluence. Additionally, as the gate length (Lg) decreased, the degradation due to DD effect increased, aggravating the degradation due to the combined effects of TID and DD. However, narrow devices with improved side gate control mitigated the effects of the interface traps, oxide traps, positive charge trapped in the spacer, and DD.

This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.

This work presents for the first time, the RF largesignal characterization of standard, high-resistivity and trap-rich substrates, along with small-signal characterization, down to the temperature of 4.2 K. These measurements mark the first instance of such characterization being performed at this temperature, using CPW transmission lines as monitor device of the substrate response. The behavior of effective resistivity, total loss and harmonic levels with temperature, evidence the RF performance enhancement of standard and trap-rich substrates below 50 K, thanks to the substrate dopants freeze-out effect. Meanwhile, highresistivity substrate performance remains stable across temperature due to the Parasitic Surface Conduction effect.

This work presents an experimental assessment of self-heating in SOI nanowire MOSFETs in ambient temperatures ranging from 300 K down to 4.2 K using the gate resistance thermometry technique. The temperature increase in the channel region is extracted, and the differential thermal resistance is obtained and plotted as a function of the device temperature. Despite the lower power dissipated by a single nanowire, the operation temperature decrease causes the temperature rise in the channel to increase from around 6 K at room temperature up to 53 K in the cryogenic range. The thermal resistance is considerably lower in nanowires than in widechannel devices, although both types of transistors present an abrupt increase in the differential thermal resistance at extremely low device temperatures.

This paper demonstrates the design process and performance prediction of a cryogenic 22 nm FDSOI circuit using a design-oriented model. The simplified EKV model is adopted to capture IV characteristics of short-channel transistors, for which parameters are extracted from cryogenic measurement of commercial FDSOI MOSFETs. When applied to a complete circuit, the model accurately predicts performances at various back-gate voltages and temperatures, achieving less than 1 % average absolute error. This validates the presented analytical approach, even under the stringent requirements of low-temperature operation, paving the way to exploiting rather than enduring cryogenic temperature effects on CMOS designs.

Due to the miniaturization of transistors, which has scaled down the channel to nanometric dimensions, the influence of parasitic elements such as series resistance has become increasingly critical to device performance. This study presents an experimental investigation of series resistance in a seven-level stacked nanosheet SOI nMOSFET. The impact of fin width, channel length, number of parallel fins, and high temperature on series resistance was analyzed. The results show that the increase in the number of parallel fins demonstrated to lower the series resistance, proportionally to the rise in conductive paths. Furthermore, narrower devices exhibit significantly higher series resistance and larger temperature sensitivity. Although the series resistance has been shown to decrease with channel length reduction, its variation with temperature has been shown to increase in shorter transistors.

Different groups worldwide have been working with the GlobalFoundries 22nm platform (22FDX) with the hopes of industrializing the fabrication of Si spin qubits. To guide this effort, we have performed a systematic study of six of the foundry's processes of reference (POR). Using effective mobility as a figure of merit, we study the impact of gate stack, channel type and back bias as a function of temperature. This screening process selected qubit devices that allowed us to couple quantum dots along both the length and width of the Si channel. We present stability diagrams with clear and regular honeycomb patterns, where spurious elements such as dopants are not observed. By combining these results with room and low temperature simulations, we provide insights into potential technology optimizations and show both the utility of qubit pre-screening protocols as well as the advantages of leveraging forward body bias within an FDSOI (Fully Depleted Silicon-On-Insulator) qubit platform.

In this study, an experimental assessment of transport parameters in 7-level stacked nanosheet GAA nMOSFETs is conducted, employing the Y-Function methodology to extract carrier mobility. Specifically, the contribution of horizontal and vertical conduction planes to mobility and degradation factors is investigated for transistors with varying channel lengths and nanosheet widths. The findings reveal that while overall low-field mobility demonstrates weak dependency on nanosheet width, it suffers some reduction in short-channel transistors. Furthermore, the mobility degradation was analyzed, and the results indicate that overall mobility degradation coefficients depend on the nanosheet width, as the balance between horizontal and vertical contributions varies. Notably, while the linear degradation factor dominates the mobility degradation at horizontal planes, vertical planes exhibit a dominant quadratic degradation factor. This suggests larger surface roughness scattering at sidewalls compared to horizontal planes.

In this paper, we explore the effect of mechanical stress on the electrical parameters, for the first time at cryogenic temperatures, using L-UTSOI 102.7 compact model. We update the model to ensure robustness and precision down to cryogenic temperatures and then we benchmark it with industrial 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFET) both at 300K and 4.2K. We observe the stress evolution with temperature through the extracted parameters of our model, which acts as a reference for the numerical mechanical simulations. The simulation provides with meaningful insights on device performance.

This paper presents cryogenic CMOS inverter-based low noise amplifiers (LNAs) for highly integrated quantum readout electronics. The circuits are fabricated in a 28-nm FD-SOI process. The LNAs consist of three stages: a first inverter stage for noise optimization, a second inverter stage for gain enhancement and a last output buffer stage for impedance matching. Four versions have been designed to cover all qubit readout sub-10-GHz scenarios. The LNAs are measured on a cryogenic on-wafer probe station at room temperature (RT: 300K) and at cryogenic temperature (CT: 4K). Thanks to the use of the back gate, the proposed circuits achieve, depending on the version, a noise figure (NF) of 1.2-2.6 dB and 0.13-0.54 dB at 300K and 4K, respectively. By pushing further the back gate voltage, a minimum NF of 0.07 dB at 4K is attained, corresponding to an ultra-low noise temperature of 4.7K.

Si-based qubits are considered the most promising experimental system for scaling quantum computing. For the first time, FDSOI CMOS technology is demonstrated as the platform to co-integrate hole and electron spin qubits with cryo-electronics. For cryo-control, we show voltage gain as high as 75dB for long devices, noise of $10^{-11} \mathrm{V}^2 \cdot \mu\mathrm{m}^2 / \text{Hz}$ and $1.29\text{mV}\cdot \mu\mathrm{m}$ threshold voltage variability. We propose a standard cell for two-qubit gates on commercial 22FDX® and show double quantum dot features. Finally, we demonstrate hole and electron qubits on the same FDSOI technology with a manipulation time below $1\mu \mathrm{s}$ and coherence time of $40\mu{\mathrm{s}}$. (Hahn echo), respectively.

This paper evaluates the electrical characteristics of Inversion-mode (IM) and Junctionless (JNT) SOI nanowire MOSFETs across a temperature spectrum from 300K to 82K. The study examines devices with varying fin widths, utilizing experimental data to analyze crucial electrical metrics, including threshold voltage, inverse subthreshold slope, and carrier mobility throughout the temperature range. The investigation also explores how these parameters are influenced by channel length and fin width.

This paper investigates the separation of the drain current components in top-bottom and sidewall currents, and the extraction of their respective low-field mobility in two-level stacked nanowire nMOSFETs. The study presents a detailed analysis of carrier transport in different crystallographic planes, emphasizing the anisotropy in mobility due to variations in sidewall roughness induced by the etching process. Devices with variable fin widths (WFIN) were measured. The effective mobility and the mobility degradation factors were extracted using the Y -function method. This study provides insights into the optimization of process and device modeling for stacked nanowire MOSFETs.

This study assesses the analog parameters of 7-level stacked SOI nanosheet transistors. The impact of nanosheet width, channel length, and bias condition is thoroughly examined through the analysis of experimental data. Key parameters, including transconductance, output conductance, and intrinsic voltage gain, are used as figures of merit for this investigation. A comparative analysis with data available in the literature reveals that the intrinsic voltage gain exhibits less sensitivity to nanosheet width when compared to single-level and 2-level stacked nanosheets.

An oxide-based random access memory (OxRAM) coupled with a MOSFET selector is widely used in memory bitcell for ReRAM technology, but the consequences of the choice of the selector parameters on the reliability are not fully understood yet. This work has the aim to provide new insights on this topic with a specific focus on scaling perspectives. Accordingly, we go through the characterization of different one-transistor one-resistor (1T1R) structures embedding the same OxRAM and selectors of different sizes where the implication of the selector in set and reset operations is separately analyzed. The set current compliance is found to be the most important metric to control the low-resistive state. The reset analysis demonstrates that the OxRAM will always switch at the same bias independently of the selector once the transistor contribution is compensated. Endurance analysis reveals that an excess of reset bias degrades the cyclability of the system. Thus, we asset that in terms of scaling, the right balance between the transistor properties and the programming conditions have to be taken into account.