Advanced concepts for photovoltaic silicon solar cells, especially high-efficiency n-type solar cells, requires appropriate wet cleaning treatment in order to remove metallic contamination prior to high temperature processes like diffusion and passivation [1]. The cost of the cleaning process should be as low as possible that requires an optimized usage of the chemicals by increasing process tank lifetimes and developing dedicated feed and bleed recipes. The just clean enough concept has been developed to fulfil the needs of PV industry to minimize the consumption of chemicals. When the dominant contamination metal is identified in quality and quantity, a dedicated wet chemical cleaning process can be applied to remove the metal concentration from the semiconductor surface under a specified limit with the minimum volume on cleaning solution. The paper describes how to optimize a dedicated wet cleaning process for prominent metal impurities like Fe, Cu, Cr, Ti, Co and Zn. For each metal an exchange volume is determined to develop a feed and bleed recipe. The accumulation of the metal impurities in the process tank is calculated and process tank lifetimes are predicted.

Silicon solar cells are the dominating technology in photovoltaics (PV) industry and have a market share of more than 85% of the modules produced for roof top installations.

Carbon nanotubes (CNT) possess excellent intrinsic characteristics like exceptionally high mechanical and conductive properties which makes them the prime candidate to reinforce high performance composite structures. However, to transfer these individual properties is still a big challenge which is often due to their bad dispersion in the matrix. The importance of CNT dispersion, their stability through-out the processing cycle, interfacial properties of CNT with different matrices are even more critical issues to finally realize the full potential of CNT. Over ten years, Nanocyl has developed a good experience to resolve these issues by following different approach such as improved innovative mixing process, CNT surface modification (functionalization) or by adding some dispersing agents or compatibilizers. Furthermore, epoxy material which is widely used as matrix for fiber reinforced composites suffers from brittleness and crack propagation. Incorporation of CNT’s was proposed as a potential technique to overcome this drawback. In the present work CNT’s are integrated with epoxy matrix in addition to unidirectional carbon fibers (CF). After dispersing CNT’s in the matrix with and without additives, unidirectional prepregs were produced subsequently composite laminates in autoclave. Mechanical tests (tensile, interlaminar shear strength-ILSS and fracture toughness) were performed. Rheological behavior of different dispersion was investigated.

3D stacked IC (3D-SIC) is one of the main approaches within 3D technologies as it is the most mature and economically viable technology and provides the highest through silicon via density. Enabling 3D SIC requires the modification of standard IC process flows by adding several process modules, such as through silicon via (TSV), wafer bonding and thinning, prior backside processing (e.g. Cu nails exposure), micro bumps formation for the front side and/or the backside and finally stacking to another chips [. Within the 3D-SIC technology developed at IMEC, surface control and preparation by means of wet clean and wet etch are essential steps notably in two key process modules: wafer thinning and micro bump formation.

The industry has diverged into two main approaches for high-k and metal gate (HKMG) integration. One is the so called gate-first. The other is gate-last, also called replacement metal gate (RMG) where the gate electrode is deposited after junctions formation and the high-k gate dielectric is deposited in the beginning of the flow (high-k first-RMG) or just prior to gate electrode deposition (high-k last-RMG) [1-. We can distinguish two RMG process flows called either high-k first or high-k last. In RMG high-k first, poly silicon is removed on top of a TiN etch stop layer whereas on high-k last poly silicon is removed on top of a dummy oxide layer. This dummy oxide has also to be removed in order to redeposit a novel high-k and work function metal (Figure 1).

A novel wet cleaning formulation approach was developed with a TiN etch rate of more than 30 Å/min at room temperature and more than 100 Å/min at 50°C. The chemicals are compatible with Cu and low-k materials, and are suitable for Cu dual damascene interconnect 28 nm and smaller technology node applications. The chemicals offer a route to in situ controlled TiN pullback or even complete removal of the TiN mask during the cleaning process in single wafer tool applications. The chemicals do not contain NH4OH or TMAH and so are very user-friendly.

In semiconductor Back-End-of-Line (BEOL) processing, wet organic strippers have gained a renewed interest for removal of etched photoresist (PR) layers to replace plasma strip, which degrades porous low-k dielectrics. In this study we show how the characterization of 193-nm PR degradation by etch plasmas led to the development of an environment friendly wet strip using aqueous ozone solutions. Characterization of post-etch PR films have shown that degradation was similar to that of poly(methyl acrylate/methacrylate) (PMA/PMMA) by UV light, with formation of single and conjugated C?C bonds in PR chains. However little removal was obtained with O"3/H"2O strips without an organic solvent rinse, indicating reactions fragments were too long for a complete dissolution in water. In turn known effects of UV on PMA/PMMA were used to develop an optimized UV pre-treatment enabling a fully aqueous O"3 strip. This process was shown to efficiently remove PR in a dual damascene application. Also we shortly discuss the impact of materials selection on process efficiency, improvement in low-k compatibility and transfer to a production environment.

Cleaning photoresist from semiconductor wafers during the transistor formation in the front end of the line (FEOL) becomes more challenging with ever smaller nodes. First of all the resists do become more difficult to clean with decreasing node size, because implantation energy increase and the resist becomes more complex (to comply with the reduced wave length of the laser light for the lithography) at future node sizes. This results in more cross linked / polymerized photoresist, which is harder to (wet) strip. Additionally, the requirements on material compatibility of the cleaning solution increase, as more elements are used to build the transistor less than a monolayer of these materials can be removed during a single cleaning step.

NMP is a commonly used solvent for removing positive photoresist in 3D applications, especially in electroplating and (micro-) bumping. However, the negative photoresists are more and more preferred in these applications. Unfortunately, NMP is inefficient for negative photoresist and it is not considered in Europe as an ESH solvent anymore. In this paper a comparative study was carried out in order to identify a solvent that is ESH friendly and a one-size-fits-all solution for stripping negative-tone and thick positive-tone photoresist (2-22 μm) for (micro-) bumping, electroplating and TSV etch applications. The study was performed at tool level.

The cumulative installed solar power generation has been rising exponentially over the past decade. This has lead to a concomitant rise in production capabilities, leading eventually to excess production capabilities and rapid price declines per unit. In order to compete with the standard electricity generation the cost of solar panel production and installation needs to decrease even further. At the same time the solar panel and cell makers need to be able to keep a healthy margin. A crucial element in this exercise is a close control on the Cost of Ownership (CoO) of a solar cell / panel fabrication site.

We report in this work some process optimization effort in performing poly silicon removal for replacement gate process integration. Successful wet poly silicon removal after dummy gate patterning is not only conditioned by suitable process conditions during wet removal but is also impacted by process steps prior to gate removal A thorough evaluation of the impact on poly removal from dopants or contaminants introduced in the poly silicon by previous processing is done, resulting in an optimized integration flow with successful poly removal. This work also shows that use of diluted TMAH chemistry instead of diluted ammonia in performing poly silicon removal provides better ability in removing poly silicon especially in narrow gate structures.

With the continuous decrease of feature size of semiconductor devices new process related challenges must be overcome continuously. One of the key issues for technology development is to have the proper metrology in place to evaluate the myriad process steps fast and accurately. Sometimes the mere existence of a particular metrology is not enough because of cost and throughput issues. The goal of this paper is to show that simply by monitoring the background signal of a light scattering tool, certain process optimizations and monitoring can be done much faster while bringing down the cost significantly. We focus particularly on post I/I strip optimization in this paper.

Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.

The production of high efficiency PV cells requires a strict control on metal contamination levels. Metals like Cu and Fe are well known to cause lifetime degradation in silicon. Analytical methodologies for determination of surface metal contamination have been well established for mirror polished, also referred to as chemical mechanical polished (CMP) silicon substrates [1]. It will be explained why these methods cannot be merely applied to photovoltaic (PV) wafers because of the large roughness and specific topography of the surface. Here we extend and adapt these analytical methodologies for surface metal contamination analysis on PV substrates also referred to as PV wafers. We demonstrate how vapour phase decomposition droplet collection (VPD-DC) in combination with total reflection X-ray fluorescence spectroscopy (TXRF) or inductively coupled plasma mass spectrometry (ICP-MS) has been modified to accommodate analysis on a non-polished PV silicon wafer surface. In addition we demonstrate how metal contamination on as-cut PV wafers has been determined by liquid surface etching (LSE), i.e. an oxidizing and slow etching solution used to dissolve metal contaminants, followed by TXRF analysis. Measurements of as-cut wafers shows the presence of Fe, Cu and Zn in very high concentrations (up to more than 1x1013at/cm2), residuals of the brass-coated steel wires used during wire sawing [10].

Atomic force microscope (AFM) with inclined sample measurement and hydrophobic functionalized AFM probe was used to visualize the sidewall of low-k pattern and allowed to characterize the hydrophobic characteristics on the sidewall after low-k etch. To functionalized the AFM probe, 1H,1H,2H,2H-Perfluorodecyltrichlorosilane (FDTS) as a hydrophobic film was coated on an AFM probe. Because of the magnitude of the phobic-phobic interaction force and the tip forced to make a phase shift. Using this technique the visualization and characterization of the etch residue on the low-k sidewall can be successfully performed. It is shown that the investigation toward an effective chemical clean for the etch residue removal could be applicable.

Tetra Methyl Ammonium Hydroxide (TMAH) was investigated for the selective removal of polysilicon in replacement metal gate (RMG) gate-last integration flow. In such application no polysilicon residues are tolerated. Therefore the TMAH process was developed using the best possible conditions by fine tuning the temperature (70ºC), concentration (5%) and process at tool level. A thorough study was conducted in order to understand the possible causes of polysilicon residues such as implantation condition (boron) and influence of the dielectric layer (SiON, SiO2, TiN) on the crystal orientation of the polysilicon. The resulting TMAH process was successfully transferred to other dummy silicon approach on TiN such as sacrificial fin. In the latter case the amorphous silicon removal was proven to be more selective towards TiN than a dry approach.

This paper discusses metal organic chemical vapor deposited (MOCVD) HfO2 layers using tetrakis(diethylamido)hafnium (TDEAH) as precursor. We have studied the influence of the starting surface and deposition temperature on the growth kinetics and physical properties of the HfO2 layers. Important characteristics such as crystalline state, density, and organic contamination in the layers were found to be dependent on these parameters. Typical for this deposition process is the formation of an interfacial layer underneath the high-k layer. Its composition and thickness, affecting scaling of the equivalent oxide thickness, are shown to be closely related to the HfO2 process parameters mentioned above. Finally, we will show electrical results for HfO2/polySi gate stacks indicating the effect for deposition temperature.

HBr plasma treatments are used to decrease surface line edge roughness (LER) of patterned photoresist (PR). In this work the modification of two 193-nm photoresists by an HBr plasma treatment was characterized by Fourier Transform Infrared (FTIR) spectroscopy, H-1-NMR (Nuclear Magnetic Resonance) and gel permeation chromatography (GPC). PR modification was shown to follow similar schemes as the degradation of poly(methyl methacrylate) (PMMA) by UV light. Beside the cleavage of ester side-groups, this study showed extensive scission of PR chains, which will contribute to LER reduction by increasing PR chains mobility. However chain scission was accompanied by cross-linking, which may put a limit to the surface-smoothening potential of this technique. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3609838] All rights reserved.

New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. However, before the 3D-stacking of IC's becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during bonding and thinning of the device wafers before stacking. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.

In this work, the lateral etching of the sacrificial high density plasma (HDP) oxide by anhydrous vapor HF (AVHF) together with ethanol vapor is characterized for SiGe microelectro-mechanical systems (MEMS) structures. An extensive design of experiment (DOE) is carried out to study the impact of the process conditions on etch rate (ER) and within wafer uniformity (UWiW). Two wafer level automated techniques, critical dimension scanning electron microscopy (CD SEM) and high resolution profiler (HRP), are compared to replace the manual inspection method performed at die level. It is found that each 25Torr increment in process pressure doubles the ER in the 75 Torr - 125 Torr range. Each 150sccm increment in AVHF flow rate increases the ER 1.3~1.5 times in the 300 sccm - 600 sccm range. Based on the reproducible ER (~80 nm/min) and the UWiW (~10%) of the process of record (POR) as measured by CD SEM, a statistical process control (SPC) is set up for this process condition.