Owing to the increasing interest in the commercialization of phase-change memory (PCM) devices, a number of TCAD models have been developed for their simulation. These models formulate the melting, amorphization and crystallization of phase-change materials as well as their extreme conductivity dependence on both electric field and temperature into a set of self-consistently-solved thermoelectric and phase-field partial-differential equations. However, demonstrations of the ability of such models to match actual experimental results are rare. In addition, such PCM devices also require a so-called selector device - such as an Ovonic Threshold Switching (OTS) device - in series for proper memory operation. However, monolithic simulation of both the PCM and OTS selector device in a single simulation is largely absent from the literature, despite its potential value for material-and design-space explorations. It is the goal of this work to first characterize a PCM device in isolation against experimental data, then to demonstrate the qualitative behavior of a simulated OTS device in isolation and finally to perform a single monolithic simulation of the PCM + OTS device within the confines of a commercially available TCAD solver: GTS Framework.

The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a resistance ~2x higher than Co when a 1.1 nm titanium nitride (TiN) film, realized by atomic layer deposition (ALD), was used as an adhesion/nucleation layer. The lowest SV resistance of 56 Ω at the median was obtained with 0.3 nm of titanium oxide (TiOx) ALD and Ru CVD. This configuration gave a 3.4x lower resistance than the equivalent scheme with 0.3 nm TiN ALD and 15% lower resistance than the stacked-via configuration (with 0.3 nm TiOx and Ru fill), meaning that an IR-drop penalty is avoided when compared to the stacked-via approach. A congestion reduction can also be expected from the CD reduction of the SVs as the exclusion area in the intermediate layer can be smaller. Thermal shock tests for both Ru and Co SVs produced no failure after 1000 cycles between −50 °C and 125 °C, and 250 hours.

Next-generation memory technologies utilizing crosspoint-array architecture require a two-terminal selector element with strong non-linearity, to suppress leakage currents. A promising candidate for this role is metal-semiconductor-metal (MSM) device, that relies on rectifying nature of Fowler-Nordheim tunneling process. In this paper, we report a detailed investigation of a breakdown mechanism of a-Si/a-Ge MSM selectors. For devices with integrated current-limiting series resistor it was found to be a non-destructive threshold switching effect, instead of a hard breakdown. The switching is field-triggered and current is area-independent after initial forming pulse, suggesting that it is closely related to ovonic threshold switching (OTS) phenomenon. Triggering current increases for thinner semiconductor and larger series resistance, providing a way to achieve higher maximum ON-current density.

The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF 63.2% (at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked.

In this abstract, we report for the first time the low-current performance enhancement combined with the improvement of the scaling potential in CBRAM devices by adopting an etch-friendly alternative material, Co, as active electrode, based on theoretical considerations and experimental results. Co is proven to yield, with respect to Cu, faster/lower voltage switching and more stable conductive filaments, irrespective of the switching layer, thanks to its higher cohesive energy. By further optimizing the switching layer, we show that the introduction of Co as active electrode is a breakthrough for boosting CBRAM performances, enabling fast and low-power switching, long endurance lifetime and optimal data retention.

The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions of minimum island, via extension and tip-to-tip (T2T). Five-track place and route (PNR) and SRAM constructions were realized with the self-aligned block (SAB) technique. Stacked vias showed resistance modulation with the size of the minimum island due to the change in via chamfer. High aspect ratio supervias (SV), to bypass M2 and directly link M1 to M3, were tested with different metallization schemes. Line-to-line and T2T reliability tests passed the 10- year lifetime predictions. Finally, electromigration (EM) tests on SV showed no failures after 140 hours of accelerated stress conditions.

We report on the reduction of leakage current at half threshold bias (I off1/2 ) down to the 1nA range achieved using Se-enriched or N-doped GeSe. Integrated 50nm OTS devices demonstrated excellent thermal stability up to 600°C, as well as electrical stability (V th , I off1/2 ) when operated at a high on current density of 23MA/cm 2 for 10 8 cycles.

We report on novel integrated Se-based Ovonic Threshold Switching selector devices, with sizes down to 50nm, which can be operated reliably at high drive current densities, exceeding 20MA/cm 2 , and have high half-bias nonlinearity exceeding well 10 3 . We show functional devices after a thermal budget of 350°C. Their electrical properties are tunable by careful control of the Ge x Se 1-x films composition, thickness or process condition.

We investigate the electronic structure and defects of Ge x Se 1-x materials at the atomic level, using full-layer-thickness (5nm) amorphous models. In Ge-rich Ge x Se 1-x , the nature of the mobility gap defects is mostly related to miscoordinated Ge. The population/localization of mobility-gap states changes solely under the effect of electric field. Strong covalent bonds introduced by N doping in the material increase its thermal conductivity and crystallization temperature beyond 600C. C/N dopants are found to add/remove mobility-gap states in the doped systems. Our investigation sets guidelines for material design in view of improved electro-thermal device performance.

We report on a novel Thin-Silicon Injector (TSI) selector concept with bidirectional operation for high density resistive switching memory. Model-based analysis shows how the current drive-nonlinearity trade-off can be broken by properly combining physical material properties to enable decoupling control parameters of the current injection from those of selectivity. We demonstrate experimentally structures down to 40nm-size, featuring a high-drive current of ~1MA/cm2, high current-voltage half-bias nonlinearity exceeding 6.103 at maximum current drive and very good reliability of >107cy endurance, with limited degradation of the selectivity. The selector has below 20nm thickness and it is fully implementable with readily available BEOL CMOS-compatible materials and processes.

We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1μs-write at ≤50μA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.

For 28-nm embedded application, we have proposed a TaO x -based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies and cell structures: low-damage etching, cell side oxidation and encapsulated cell structure. As a result, we succeeded for the first time in forming a filament at the cell center. In addition, we confirmed the feasibility of 20-nm cell size. Excellent reliability was achieved in 2-Mbit 40-nm ReRAM: 100k cycles and 10 years' retention at 85°C was demonstrated.

We engineer a scalable and CMOS-friendly RRAM stack using down to 3nm ALD-based Ta 2 O 5 . The 20nm-sized TiN\Ta 2 O 5 \Ta device operated at 50μA exhibits ultra-fast write (~5ns) at moderate voltage (<;2V) with >10 9 write endurance. We also demonstrate excellent disturb and retention characteristics, which we relate to the appropriate tuning of the oxygen chemical-potential profile along the filament by means of the Ta scavenger material and thickness.

In order to improve the characteristics of future integrated circuits, low dielectric constant (low-k) materials are employed. In this paper we describe in detail the characteristics of k = 2.0, SICOH films treated by capacitively coupled Ar/N-2 and Ar/H-2 plasmas, which were applied in order to modify the top surface of the film. New insights were obtained about the porous structure of the pristine and the plasma treated films: analyses indicated that the investigated plasma treatments reduced the pore size in the top ten nm of the films, while partial carbon depletion was found down to a few tens of nm inside the film. For the integration of metal barriers deposited by Atomic Layer Deposition in interconnect technologies, precursor penetration into the porous low-k dielectric should be avoided. We investigated precursor penetration in the pores during TaN Atomic Layer Deposition on the pristine and the plasma treated porous low-k films. Detailed analyses showed that the plasma induced modifications resulted in a local growth enhancement and pore sealing during the first cycles of the atomic layer deposition process. (C) 2013 The Electrochemical Society.

2013 International Conference on Solid State Devices and Materials,Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

Atomic layer deposition is a promising technique to deposit conformal, nm-thin metal barriers in high-aspect-ratio trenches. However, exactly because of its excellent conformality, the deposition can also occur inside the nanopores of the most advanced low-k materials. In this work, the mechanisms of atomic layer deposition on and in low-k, porous dielectric films were studied, using HfO2 as a test material. Exhaustive analyses showed firstly that the HfCl4 precursor penetrated uniformly in the pores throughout a 44 nm thick low-k film. Secondly, it was shown that the pores were sealed as function of precursor size, i.e. there are conditions where the pores became inaccessible for HfCl4, while the - smaller - H2O molecules could still penetrate the pores. From these analyses, a deposition model was proposed. (C) 2013 Elsevier B.V. All rights reserved.