Semiconductors are the invisible engine behind modern life, powering everything from smartphones to cloud infrastructure. Modern microprocessors, integrated advanced chiplet architectures, 3D packaging, and artificial intelligence (AI) acceleration are all made possible by cutting-edge logic transistor and interconnect technologies. Leading-edge products are a snapshot of where the semiconductor roadmap is headed. This roadmap explores the evolution of logic technology from fin field-effect transistors (FinFETs) to gate-all-around (GAA) transistors and beyond. GAA offers improved gate control and scalability, but as contacted poly pitch (CPP) scaling slows, the industry is shifting focus to vertical scaling and interconnect innovation. Back-side power delivery networks (BSPDNs) and ruthenium-based subtractive interconnects are emerging as key enablers for future nodes, addressing the growing challenges of resistance, capacitance, and routing congestion. Looking forward, transistor stacking—particularly complementary FET (CFET) architectures—promises to extend Moore’s law by increasing density without shrinking lateral dimensions. Multiple integration flows, including monolithic, sequential, and wafer bonding, are being explored to realize this vision. Hybrid bonding further expands the design space, enabling static random-access memory (SRAM) and logic stacking. As scaling reaches atomic dimensions, cross-disciplinary efforts in design–technology co-optimization (DTCO) are essential. The future of semiconductors will be shaped not just by shrinking features but by reimagining how devices are built, stacked, and powered—continuing the legacy of innovation.

An advanced Intel 3 FinFET technology is presented that has been optimized to provide 10% logic scaling, a full node of performance improvement and improved reliability compared to Intel 4. Through transistor enhancements, interconnect optimization, and design co-optimizations, up to 18% performance gain at iso-power is achieved over Intel 4. Intel 3 additionally enables a 210nm high-density standard cell, 1.2V-native I/O transistors, deep N-well isolation, and long-channel analog devices to provide full-featured technology design capabilities.

We present a high density MIM decoupling capacitor that enables improved microprocessor performance by providing robust on-chip power supply droop reduction. The MIM dielectric is fabricated using ALD-deposited HfO2-Al2O3 and HfO2-ZrO2 high-k dielectrics with PVD TiN electrodes. We achieve single MIM-cap densities of 37 fF/μm2 and 52 fF/μm2 that meet reliability requirement for both 1.98 V and 1.26 V use conditions. The reliability of the HfO2-ZrO2 capacitor shows minimal voltage polarity dependence, which enables the use of multi-plate MIM-caps to increase capacitance density. We achieved a capacitance density of 141 fF/μm2 with a four-plate configuration, representing a 3.5× improvement over the reported capacitance density on Intel’s 14 nm process. In addition, the stack meets environmental stress tests. This MIM- cap improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.

We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.

This paper discusses the reliability of a new metallization scheme for 10nm back end of line (BEOL) local interconnect. Electromigration (EM) and time dependent dielectric breakdown (TDDB) on cobalt fill interconnects are investigated. Significant innovation in process manufacturing are delivered to meet the reliability challenges of technology scaling. Electromigration time to failure is observed to be at least four orders of magnitude higher for Co fill interconnects compared to Cu alloy metallurgy. Intrinsic TDDB reliability for Co/low-k ILD meets the expectations and surpasses the capability of Cu/low-k ILD systems with E-field acceleration factor of ~5 cm/MV using E-model fit. Wafer level stress induced voiding reliability on Co shows superior intrinsic properties with respect to Cu.

This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduced to continue Moore's Law, i.e. sub-40nm interconnect pitches to enable 10nm node cells that include 34nm fin pitch and Contact-over-active-gate (COAG) layout. Cobalt metallization is introduced in the pitch quartered interconnect layers in order to meet electromigration and gapfill-resistance requirements.

A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5 th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology.

A summary of NBTI variation is reported on large data-sets across five generations of Intel technologies (90 nm to 22 nm) and a comparison of statistical frameworks is utilized to show the universality of variation metrics across generations. Large volumes of data and modeling are emphasized as critical to enable accurate simulations of NBTI in extreme tails.

This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3 rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3 rd -generation high-k + metal-gate technology and a 5 th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (~70mV/dec) and very low DIBL (~50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process. Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (~70 mV/decade) and very low DIBL (~50 mV/V) values that are critical for low voltage operation. Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch. This enables an SRAM cell size of 0.092 μm2. High yield and reliability have been demonstrated on multiple microprocessors.

June 12, 2012 – Intel Corporation is delivering myriad presentations, panel discussions and demonstrations at this year’s VLSI Symposia. A highlight paper discloses new details about Intel’s 22nm process – the industry’s first fully depleted 3-D tri-Gate technology with superior low voltage and low power capabilities. Other Intel papers describe innovations in reducing power consumption for graphics processing, advances in transistors made with compound semiconductors, a viable option for future ultra-low power transistors, fundamental leaps in energy-efficient computing and integrated digital radio and SoC technology.

Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore's law.

Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45 nm high-k + metal gate technology.

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.