The enablement of a high-density memory array in a System on Chip (SoC) is a great opportunity to overcome the Von-Neuman bottleneck in computation, especially for applications at the edge. In this work, we will show that a dense array based on 0.019μm2 Phase-Change-Memory (PCM) cell, embedded in 18nm FD-SOI CMOS process, typically operated in differential mode, can be operated in single-ended mode for effectively storing Neural Network (NN) weights on a wide range of mission profiles. Differently from the previously adopted differential approach, the single-ended is less resilient to PCM reliability mechanisms, so proper algorithm and design optimizations have been carried out to provide a reliable behavior.

In this paper, the competitive advantage of Phase Change Memory (PCM) with BJT selector in 18nm FDSOI technology is explained. Starting from Microcontrollers requirements and architectures, the impact of technology features and device flavor in high performance and low-cost Microcontrollers is analyzed in section I, while the peculiarities of ePCM cell with BJT selector and its high-density advantages vs other NVM Back End solutions are illustrated in section II. The ePCM NVM IP Architecture constraints are presented in section III with particular emphasis on the need to split the arrays in Tiles. In section IV the impact of BJT selector in Reading Architecture is discussed showing the limits of classical solution and introducing a reading technique using multiple voltage domains sensing for Low Power Micros. Experimental results on a dedicated Test Vehicle are illustrated in section V.

The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

One of the most promising Embedded Phase Change Memory (ePCM) integration scheme is the wall architecture, which relies on the dedicated Heater element to thermally switch the device. A good control of this element is a key factor to satisfy the performance requirements of the automotive market. In this paper, the optimization of TiSiN Heater system in $0.019\mu \mathrm{m}^{2}\text{ePCM}$ cell realized with 28nm FDSOI technology is extensively reported. Key fabrication parameters defining heating efficiency are investigated, covering a large range of Heater resistance. Their impact on $e$ PCM reliability of elementary device and 16MB memory array, considering both retention and endurance, is characterized and the key role played by Heater is demonstrated, opening a path to scaled programming currents. Finally, TiSiN ALD deposition process is proposed as the solution to improve uniformity and scalability of Heater resistance. As Heater is the variable controlling the whole system, this approach guarantees the robustness of $e$ PCM technology for automotive grade-0 applications.

Fabrication and electrical characteristics of a new BJT selector enabling a 1T1R embedded phase change material (ePCM) memory cell of 0.019µm 2 are extensively reported in this paper. A smart process, leveraging the specific feature of the FDSOI substrates with its thin buried oxide (BOX) has been developed to create an innovative isolation wall between bitlines (BL) and to totally suppress the parasitic BL-to-BL leakage. A current of 300µA at V EB =1.6V and a leakage as low as 8pA/cell at V BE =3.6V, 165°C were achieved. Compared to its MOS selector counterpart, -48% cell area reduction is obtained at same driving current, demonstrating the high density and the cost competitiveness of this FDSOI BJT selector solution. Finally, a shrunk BJT-ePCM cell of 0.015µm 2 , which is the smallest 1T1R eNVM reported to date, is demonstrated for the first time.

This paper discusses the effect of back-end of line (BEOL) process on cell performance for a Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM). The impact of BEOL is first shown by describing the microscopic evolution of the active Ge-rich GST alloy during process. Ge clustering has been proven to occur during the fabrication process, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is then identified, and an extensive electrical characterization of array performance and reliability is performed on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

A comparative analysis of different Resistive Memories proposed as Non Volatile Memories for embedded applications is here presented. Based on today scenario of industry-standard Floating Gate solutions, key factors as performances, reliability and technology maturity are considered when facing more innovative memory cells. In particular the race seems to be open at 28nm, where different players are proposing different memories integrated in the Back End Of the Line. Original results obtained on multi-megabits array integrating Phase Change Memories are here discussed covering cell scalability, High Temperature data retention and extended endurance capability, all in line with eNVM application requirements.

The eStM (embedded Select in Trench Memory) is a floating gate based non-volatile memory cell conceived, developed and industrialized by STMicroelectronics for General Purpose and Secure Microcontrollers embedded applications. Thanks to its unique architecture, the eStM cell gathers the advantages of a conventional split-gate NVM cell together with a more compact cellbit area than a typical 1T Flash Memory cell, and it is claimed to represent the scalability limit for a floating gate based NOR NVM.

In this chapter, we will highlight the peculiar features of one of the most popular implementations of the embedded flash cell: the so-called 1Tr-NOR. The one-transistor cell has been by far the most adopted cell architecture in the world of flash NORNOR stand-alone memory. As an almost natural consequence, 1Tr-NOR architecture has also been considered the first, and for sure one of the best, solutions in embedded non-volatile memory (NVM) applications and has been progressively replacing EEPROMEEPROM cells. In this chapter, only embedded multi-megabit flash implementation will be reviewed: different solutions for 1Tr-NOR flash cell structure and design architectures have been successfully implemented and will be described. In particular, the focus hereinafter is based on the description of how the unique features offered by that cell can be efficiently and effectively integrated into MCUsMicro-Controller Unit (MCU) , which represent one of the major fields fueled by embedded flash capability. In the following sections, after a short introduction devoted to highlighting some peculiar technology features related to 1Tr-NOR integration with state-of-the-art CMOS, three different kind of MCUMicro-Controller Unit (MCU) products will be thoroughly analysed: