An IMC based low temperature solder <200 °C with AuInSn composition is developed for 3D IC stacking application. Thermodynamic and mechanical simulations are conducted to study the phase change during the melting temperature and the stress due to the thin solder material. A three layer stack bonding with the developed solder has been characterized after bonding and reliability test. It is found that no degradation in shear strength and compositional structure of the solder and is verified by the TEM cross sectional structure with EDX analysis. A 3D IC structure with TSV test vehicle is designed and demonstrated the low temperature solder application. C2W bonding approach is used for the 3D IC stack bonding method and is found suitable for devices with TSV structure. Final reliability test with daisy chain structure and TSV showed <10% resistance increase in majority of interconnections after 1000 cycles of thermal cycle test.

A passive magnetostatic microelectromechanical systems (MEMS) switch using only one electroplated soft magnetic layer of nickel-iron (Ni 80 Fe 20 ) alloy was designed, fabricated, and characterized. The switch is composed of an electroplated Ni 80 Fe 20 plate supported by a pair of torsion bars from two sides. The Ni 80 Fe 20 plate is patterned into long and narrow strips to improve the sensitivity. The switch is actuated by bringing an external magnet closer to the switch. Therefore, no internal electrical power is consumed by the device for actuation. The magnetic field required to turn on the switch is 4.8 mT, and the initial contact resistance is 0.5 Ω with gold contacts. The switch has been tested to pass more than 34 million hot-switching cycles at 2-mA current at room temperature when packaged at the wafer level with SU-8 sealing. The die size is 2.1 × 1.94 × 1.1 mm 3 . The magnetic switch of this paper has the potential to replace the conventional reed switch in portable electronics such as laptops, cellular phones, personal data assistants, pacemakers, and hearing aids.

A passive MEMS magnetostatic relay using only one electroplated magnetic layer was presented. The relay consists of an electroplated Ni80Fe20 plate supported by a pair of torsion bars from two sides. The relay is actuated by approaching an external magnet to the relay. The switching-on magnetic field is about 4.8 mT and the contact resistance is about 3 ohms with gold contact. The lifetime testing shows more than 7.5 million hot switching cycles with 1-2 mA current. This passive magnetic relay could find applications in portable electronics, such as cellular phones, personal data assistant (PDA), pace makers, hearing aids, etc.

A dry film photoresist was selected as the sacrificial material for a metal lift off process. However, a weak and inconsistent adhesion of the evaporated under bump metallurgy (UBM) and solder on the passivation surface was observed during the dry film stripping process. This problem may be due to the poor negative profile (88 to 89 degrees) of the patterned dry film side wall after dry film developing, resulting to inconsistent metal lift off. A few dry film predevelopment and post development parameters are identified and tested from the standard dry film development process, to obtain a negative profile of the dry film to be less than 84 degrees. After each test, cross section of the patterned dry film side wall is observed under a microscope to check if a negative profile is obtained. The 50 mu m thick dry film at 35mJ/cm(2) with other modifications of the process gives the best results

In this paper, through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200 um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200 degrees C forming robust intermetallics (MC) joints with high re-melting temperature (>300 degrees C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as such chips are temporary bonded onto wafer before the final bonding. The chips are bonded onto the wafer by two sequential bonding condition; temporary followed by a final bonding, which is 200/90 degrees C (chip/wafer) for 20sec and 180/180 degrees C for 5mins. The IMC joints are evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. These IMC joint showed a tensile strength of 120 similar to 330N (23.5 similar to 38.8MPa). Based on this study, the 3 stacked dice with 8x8 mm(2) dies with similar to 1700 I/Os of 80um solder bumps were fabricated in a chip to wafer stacking method. It showed uniform bonding all over the die in each layer with relatively good tensile strength achieved. Furthermore, it also underwent 3 times reflow test at 260 degrees C. The IMC joint was examined after going through the reflows test and the bonded samples exhibited neither de-lamination nor any changes in the microstructure.

The development of a low-insertion-loss bandpass filter and a dipole antenna using wafer transfer technology (WTT) for 60-GHz band applications is presented for the first time. The WTT process provides a much higher fabrication accuracy than the traditional printed circuit board/thick-film process. In addition, the WTT also provides a new way to transfer millimeter-wave circuits from the high-loss Si substrate to low-loss microwave substrates like the Rogers RT/Duroid 5880. The bandpass filter has a measured 3-dB bandwidth of 12 GHz, and the measured minimum insertion loss is 1.8 dB. The dipole antenna has shown a measured frequency bandwidth from 56 to 61.5 GHz for |S11| less than -10 dB and a measured gain of 5.1 dB at 60 GHz. Compared with the integrated bandpass filter and antennas on CMOS, the WTT shows to be very promising for 60-GHz applications.

Low temperature bonding technology was developed using In-alloy on Au at a low temperature below 200degC forming robust intermetallics (IMC) joints with high remelting temperature (>300degC), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Process parameters on the solder joint were optimized extensively in bonding and annealing process (temperature, time, and pressure). The joint fabricated at an optimal condition, which is 180degC for 45sec followed by annealing at 120degC for 12hrs, was evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. And the re-melting temperature was measured as above 400degC by using Differential Scanning Calorimetery (DSC) and Thermo-Mechanical Analysis (TMA). This IMC joint showed a high bonding shear strength (>20MPa) and a low electrical resistance (<100mOmega). Based on this study, the 3 stacked dice with 8times8 mm2 dies with ~1700 I/Os of 80um solder bumps were fabricated in a chip to chip stacking method. It showed uniform bonding all over the die in each layer and the high bonding strength of ~40 MPa and passed the 3 times reflow test at 260degC. The IMC joint reliability was examined. After going through the multiple reflows at 260degC, the bonded samples exhibited no delaminating and no changes in the bonding strength and the electrical resistance.

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.

This paper provides a detailed overview of silicon carrier based packaging for 3D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a 3-step approach has been developed and characterized which controls via depth, sidewall profile and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.