We investigate the operating conditions under which networks of coupled phase-locked Ring Oscillators can successfully map to Ising models in order to efficiently solve optimum search problems, shedding light on the fundamental design space trade-offs impacting solution quality. We designed and experimentally measured a test chip in 22nm FD-SOI technology with built-in readout. By solving various fully-connected 5-node graphs encoding 3-level Weighted MAX-CUT problems, we discuss the challenges associated to balancing the relative strength of coupling and synchronization signals.

We report on a novel technique for localized interface passivation in High-Resistivity (HR) silicon-based substrates. Called Field Effect Depletion Regions (FEDR), it relies on alternating dielectrics with fixed charge densities of different signs Q ox, pos and Q ox, neg near the substrate interface to passivate the Parasitic Surface Conduction (PSC). TCAD simulations based on a Coplanar Waveguide (CPW) structure on FEDR-passivated HR substrates describe the substrate response against fixed charge density, pattern pitch and DC bias variations. It is shown that in the best cases, FEDR enables maintaining roughly one order of magnitude improvement on the substrate effective resistivity versus unpassivated HR up to $100 GHz \rho_{\text{eff}}\sim 1\ \mathrm{k}\Omega\ \text{cm}$ . Moreover, this work provides some guidelines on finding the best pattern periodicity while respecting technology constraints.

We study recurrent networks of binary stochastic Magnetic Tunnel Junctions (sMTJ), aiming at efficiently solving computationally hard optimization problems. After validating a prototyping route, we investigate the impact of hybrid CMOS+MTJ building block variants on the quality of stochastic sampling, a key feature for optimum search in a complex landscape. In this regard, a better decoupling of the read/write paths gives spin-orbit torque (SOT) sMTJs an advantage over two-terminal spin-transfer torque (STT) sMTJs. We carry out a functional and power consumption analysis on asynchronous Ising networks in which coupling occurs through arrays of resistors, in the frame of Boolean satisfiability (SAT) solving. Using our SPICE model, we demonstrate that a 48-node SOT sMTJs network successfully converges to its ground state, factoring an 8-bit integer in 10μs with an estimated power consumption of 133μW/node.

Three key metrics for readout systems in quantum processors are measurement speed, fidelity and footprint. Fast high-fidelity readout enables mid-circuit measurements, a necessary feature for many dynamic algorithms and quantum error correction, while a small footprint facilitates the design of scalable, highly-connected architectures with the associated increase in computing performance. Here, we present two complementary demonstrations of fast high-fidelity single-shot readout of spins in silicon quantum dots using a compact, dispersive charge sensor: a radio-frequency single-electron box. The sensor, despite requiring fewer electrodes than conventional detectors, performs at the state-of-the-art achieving spin read-out fidelity of 99.2% in less than 6 $\mu$s. We demonstrate that low-loss high-impedance resonators, highly coupled to the sensing dot, in conjunction with Josephson parametric amplification are instrumental in achieving optimal performance. We quantify the benefit of Pauli spin blockade over spin-dependent tunneling to a reservoir, as the spin-to-charge conversion mechanism in these readout schemes. Our results place dispersive charge sensing at the forefront of readout methodologies for scalable semiconductor spin-based quantum processors.

Silicon offers the enticing opportunity to integrate hybrid quantum-classical computing systems on a single platform. For qubit control and readout, high-frequency signals are required. Therefore, devices that can facilitate its generation are needed. Here, we present a quantum dot-based radiofrequency multiplier operated at cryogenic temperatures. The device is based on the non-linear capacitance-voltage characteristics of quantum dot systems arising from their low-dimensional density of states. We implement the multiplier in a multi-gate silicon nanowire transistor using two complementary device configurations: a single quantum dot coupled to a charge reservoir and a coupled double quantum dot. We study the harmonic voltage conversion as a function of energy detuning, multiplication factor and harmonic phase noise and find near ideal performance up to a multiplication factor of 10. Our results demonstrate a method for high-frequency conversion that could be readily integrated into silicon-based quantum computing systems and be applied to other semiconductors.

We investigate the temperature-dependent RF response of different types of silicon substrates (standard, high-resistivity and trap-rich) through measurements performed on BEOL-embedded inductors from room temperature down to 7K. For the first time, we observe that the performance ranking between substrates, well known at 300K, is altered in cryogenic conditions (T<50K). Based on a parametric analysis of the Q-factor, we attribute this behavior to the heightened importance at low T of counteracting a parasitic surface conduction (PSC) forming at the interface between the substrate and the dielectric.

Strain is extensively used to controllably tailor the electronic properties of materials. In the context of indirect band-gap semiconductors such as silicon, strain lifts the valley degeneracy of the six conduction band minima, and by extension the valley states of electrons bound to phosphorus donors. Here, single phosphorus atoms are embedded in an engineered thin layer of silicon strained to 0.8% and their wave function imaged using spatially resolved spectroscopy. A prevalence of the out-of-plane valleys is confirmed from the real-space images, and a combination of theoretical modelling tools is used to assess how this valley repopulation effect can yield isotropic exchange and tunnel interactions in the $xy$-plane relevant for atomically precise donor qubit devices. Finally, the residual presence of in-plane valleys is evidenced by a Fourier analysis of both experimental and theoretical images, and atomistic calculations highlight the importance of higher orbital excited states to obtain a precise relationship between valley population and strain. Controlling the valley degree of freedom in engineered strained epilayers provides a new competitive asset for the development of donor-based quantum technologies in silicon.

In this paper, we aimed to show the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (rho(eff)) figure of merit of a High-Resistivity (HR) substrate suffering from Parasitic Surface Conduction layer (PSC). We characterize Coplanar Waveguides (CPW) in order to monitor the substrate frequency response. We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2 k omega.cm with 0.1 dB/mm loss at 6 GHz for a HR + PN substrate. PN pattern, temperature and implantation conditions varations were performed in order to identify the buried PN junctions robustness. At high-temperature, HR + PN substrate still shows an enhancement of RF performance. Contrary to HR w/o PN, HR + PN is bias independent. This method is suitable for local PSC passivation, targeting advanced SoC (System-on-Chip) in FD-SOI technology for next wireless communication generations and embedded RF electronics.

Semiconductor spin qubits based on spin-orbit states are responsive to electric field excitation allowing for practical, fast and potentially scalable qubit control. Spin-electric susceptibility, however, renders these qubits generally vulnerable to electrical noise, which limits their coherence time. Here we report on a spin-orbit qubit consisting of a single hole electrostatically confined in a natural silicon metal-oxide-semiconductor device. By varying the magnetic field orientation, we reveal the existence of operation sweet spots where the impact of charge noise is minimized while preserving an efficient electric-dipole spin control. We correspondingly observe an extension of the Hahn-echo coherence time up to 88 $μ$s, exceeding by an order of magnitude the best reported values for hole-spin qubits, and approaching the state-of-the-art for electron spin qubits with synthetic spin-orbit coupling in isotopically-purified silicon. This finding largely enhances the prospects of silicon-based hole spin qubits for scalable quantum information processing.

Semiconductor-based architectures where quantum information is encoded in the spin degrees of freedom of electrons or holes form an appealing platform for quantum computing. Here we present the current state-of-the-art and discuss prospects and challenges at scientific and technological level.

We report the first experimental proof of concept of a new electromechanical adiabatic logic family operating without any kind of electrical and mechanical contacts. Based on comb-drive actuators and standard microelectromechanical system (MEMS) microfabrication, we demonstrate the cascadability of logic gates up to 170 °C, and operation in the kilohertz-range under a power supply of 4.5 V. Assuming that state-of-the-art microfabrication can downscale our MEMS gates by a factor of 100, we expect a dissipation of 0.1 aJ/op (24 $\text{k}_{\text {B}}\text{T}$ ) at 250 kHz at 45 mV. This study paves the way toward new reliable low-power electromechanical digital circuits.

We present recent progress in the implementation of scalable schemes for spin qubit readout in one dimensional quantum registers based on fully-depleted silicon-on-insulator (FDSOI) technology. We compare two schemes both based on rf gate reflectometry. The first one, denoted as dispersive readout, minimizes the device overhead thereby facilitating scale-up to large qubit registers. The second one, denoted as charge-sensing readout, requires additional readout components but is less sensitive to the strength of the interdot coupling facilitating operation in the few-electron regime. We demonstrate single-shot charge sensing with a fidelity of 97% in 5 μs. Finally, we propose a scalable device architecture for linear qubit registers relying on charge-sensing readout.

We discuss the status, challenges and perspectives of "Quantum CAD" for the design and exploration of spin qubits. We highlight the similarities and differences with conventional TCAD for micro-electronics, and focus on design, physics and variability of silicon-on-insulator qubits as an illustration.

Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers a compact and scalable readout with high fidelity, however, further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier, that operates in the 500-800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio, we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in 1  μs, well below the requirements for fault-tolerant readout and 30 times faster than without the Josephson parametric amplifier. Additionally, the Josephson parametric amplifier allows operation at a lower radio-frequency power while maintaining identical signal-to-noise ratio. We determine a noise temperature of 200 mK with a contribution from the Josephson parametric amplifier (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the readout speed.

We report the efforts, challenges and perspectives dedicated towards building a reliable spin read-out for Si spin qubit systems. We review several strategies that are pursued in the semiconductor quantum circuit community. We discuss their pros and cons with respect to their performance (speed and fidelity), their integration potential and their footprint. We then address the envisioned architecture to read-out spin qubits at large scale.

We show how to measure and manipulate a single spin in a CMOS device fabricated in a pre-industrial 300 mm CMOS foundry. The device can be used as a spin quantum bit working at very low temperature. The spin manipulation is done by a microwave electric field applied directly on a gate. The presented results are a proof-of-principle demonstration of the possibility to define qubits by means of conventional industrial fabrication processes.

Silicon-based quantum bits with electron spins in quantum dots or nuclear spins on dopants are serious contenders in the race for quantum computation. Added to process integration maturity, the lack of nuclear spins in the most abundant (28)silicon isotope host crystal for qubits is a major asset for this silicon quantum technology. We have grown (28)silicon epitaxial layers (epilayers) with an isotopic purity greater than 99.992% on 300 mm natural abundance silicon crystals. The quality of the mono-crystalline isotopically purified epilayer conforms to the same drastic quality requirements as the natural epilayers used in our pre-industrial CMOS facility. The isotopically purified substrates are now ready for the fabrication of silicon qubits using state-of-the-art 300 mm Si CMOS-foundries equipments and processes.

Silicon spin qubits have emerged as a promising path to large-scale quantum processors. In this prospect, the development of scalable qubit readout schemes involving a minimal device overhead is a compelling step. Here we report the implementation of gate-coupled rf reflectometry for the dispersive readout of a fully functional spin qubit device. We use a p-type double-gate transistor made using industry-standard silicon technology. The first gate confines a hole quantum dot encoding the spin qubit, the second one a helper dot enabling readout. The qubit state is measured through the phase response of a lumped-element resonator to spin-selective interdot tunneling. The demonstrated qubit readout scheme requires no coupling to a Fermi reservoir, thereby offering a compact and potentially scalable solution whose operation may be extended above 1 K.

We fabricated linear arrangements of multiple split-gate devices along an SOI mesa, thus forming a 2×N array of individually controllable Si quantum dots (QDs) with nearest neighbor coupling. We implemented two different gate reflectometry-based readout schemes to either probe spin-dependent charge movements by a coupled electrometer with single-shot precision, or directly sense a spin-dependent quantum capacitance. These results bear significance for fast, high-fidelity single-shot readout of large arrays of foundry-compatible Si MOS spin qubits.

This paper reports the study, design, and simulation of a symmetrical comb-drive actuator. The approach for definition of the potential energy of the system is proposed. The electrical parameters of the comb-drive actuator are defined in COMSOL Multiphysics® software. Depending on an actuation voltage and an initial design it can form system with one, two, and three stable states. We show that the equilibrium at x = 0 is more stable for the comb-drive actuator with positive overlap than for device with the gap of the same value. The proposed approach will be used for design of the symmetrical actuator, which forms the output of the recently proposed contactless four-terminal MEMS element for capacitive adiabatic logic based on silicon MEMS technology.