It was found that applying a capping layer has an important impact on the work function (WF) of Mo gated metal-oxide semiconductor stacks. Before any postmanufacturing thermal treatment, uncapped Mo has a similar WF as one capped with a TaC layer. However, after forming gas anneal (FGA), the uncapped Mo gate exhibits a significantly higher WF than the TaC capped one does. This is understood as O incorporation during deposition, storage or FGA, and its subsequent piling up at the Mo/dielectric interface during FGA in the former case, which is an effect prevented by TaC capping.

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

The interaction between the dielectric and the metal gates is crucial for effective workfunction and V"T. In this work, we investigate the effect of a degas step just before the metal gate deposition. The purpose of this step is to remove the water adsorbed at the surface of the dielectric by heating it under vacuum. Removing the water also means the suppression of an O source during following processing steps of the device. This leads to lower oxygen vacancies passivation. When the maximum of water is removed from the surface, NMOS long channel V"T is decreased and PMOS long channel absolute V"T is increased. From the dielectric point of view, degassing leads to lower intrinsic quality as measured by gate leakage increase as a function of the temperature.

In this paper it will be shown that the deposition method is an important parameter for the electrical properties of the metal gate. Indeed, ALCVD(Atomic Layer Chemical Vapor Deposition) TiN metal has a 5.3eV workfunction, suitable for PMOS devices. The PVD sputtered (Physical Vapor Deposition) TiN has a lower workfunction around 4.8eV and is mid-gap like. The PVD TiN capacitors have a higher effective oxide charge than the ALCVD capacitors as extracted from capacitance measurements and from workfunction calculations. PVD TiN also exhibits process-induced damage as seen from leakage measurements.