This paper discusses metal organic chemical vapor deposited (MOCVD) HfO2 layers using tetrakis(diethylamido)hafnium (TDEAH) as precursor. We have studied the influence of the starting surface and deposition temperature on the growth kinetics and physical properties of the HfO2 layers. Important characteristics such as crystalline state, density, and organic contamination in the layers were found to be dependent on these parameters. Typical for this deposition process is the formation of an interfacial layer underneath the high-k layer. Its composition and thickness, affecting scaling of the equivalent oxide thickness, are shown to be closely related to the HfO2 process parameters mentioned above. Finally, we will show electrical results for HfO2/polySi gate stacks indicating the effect for deposition temperature.

Targeting very thin equivalent oxides (<1 nm) requires the deposition of (very) thin dielectrica onto silicon surfaces with minimal interfacial oxide. Typically, high-k dielectric layers are deposited using ALD or MOCVD with, at present, a prime emphasis on Hf-based high-k dielectrics, either as pure HfO2, as silicate or mixed with Al2O3. In some cases nitrogen is added to improve the high-temperature stability. Depending on the deposition conditions ALD as well as MOCVD show serious deficiencies in terms of film closure and material density for ultra thin (<3 nm) films. Various surface preparation methods and deposition conditions are used to improve the film quality.. Detailed studies on the film growth and its evolution requires the use of many analytical methods such as Rutherford Backscattering Spectrometry, Low Energy Ion Scattering, Time-of-flight SIMS, (spectroscopic) ellipsometry and X-ray photoelectron spectroscopy. When trying to correlate the results in terms of film thickness, apparent discrepancies can be observed which relate to non-homogeneous growth and reduced material density.

We demonstrate multi-VT engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling VT tuning without any device degradation. It is shown that this approach is suitable for multi-VT engineering with aggressively scaled dielectrics and, particularly, for fully depleted 3D device architectures.

Easily integrable cost effective gate first Single Metal Single Dielectric (SMSD) solution based on As implantation into TiN/HfO 2 with ∼ 1 nm EOT is presented. A consistent n-type shift of 250 mV down to 35 nm L g is obtained by As I/I compared to the reference stack. Symmetrical threshold voltages (∼ ±0.5 V) are met for the bulk planar devices using this technique, which would corresponds to low-V T (±0.2V) target for the FD FETs. The possible counter-doping effects were evaluated electrically and physically with backside SIMS. It was found to be negligible implying negligible concentration of As in the channel region. As I/I technique opens up possibility of multiple V T tuning without adding any process complexity.

Two SMSD gate first planar CMOS devices were demonstrated. Vtn/Vtp= +0.49V/-0.48V were achieved by adjusting TiN to p-like metal and As I/I on nMOS. This enables the equivalent +/-0.2V low Vt target of N22 fully depleted CMOS technologies. Vtn/Vtp= 0.52/-0.55 were obtained by transforming PVD-TiN/Ti into n-like metal TiN/TiSix for nMOS and by Al I/I on TiN/Ti for pMOS. Al diffusion was facilitated by snowplow effect of TiSix formation on pMOS. As low as 7.3A EOT with decent Jg 6.4E-3 A/cm 2 @ 1.1Vwas obtained.

First principles calculations of the impact of Al incorporation on the effective work function of a TiN/HfO2 interface are presented. The undoped interface has a midgap effective work function. We find that Al in the metal and Al substituting for O in the dielectric make the effective work function more n-type. More importantly, Al substituting for Hf in the oxide near the interface—the energetically stable position for most growth conditions—increases the effective work function, making it more p-type. Furthermore, the shift of the work function increases with increasing the Al concentration at the interface. The calculated results are consistent with experimental data.

In the framework of fully depleted devices, we report up to 150 mV V T tuning towards the Si conduction band by implantation of Te into molybdenum capped with TiN, the dielectric being HfO 2 . Moderate post implant anneal seems to have no effect on the V T shift while high temperature anneal is needed to shift the EWF significantly. The temperature applied to the devices during the entire process is therefore crucial for driving the implanted species towards the Mo/high-k interface, where they can modify the interface dipole and hence modify the effective workfunction. Hence, high temperature standard pike anneal is a very interesting option. The effective workfunction shifts linearly with the dose. Moreover, the higher the implant energy, the larger the effect of the dose on the effective workfunction. Up to 10 keV, the device integrity is preserved after ion implantation. At higher energies, implanted ions penetrate into the high-k, which leads to D it and subthreshold slope degradation. However, there is no evidence of counterdoping in this later case and gate leakage is hardly increased.

We investigate the influence of aluminum oxide (AlO) capping on SiON on the threshold voltage and I-on of Poly-Si/TiN gated pMOSFETs. The AlO capping resulted in threshold voltage (V-T) reduction and improvement in drive current (I-on) for Poly-Si/TiN/ gated pFETS. The AlO capping on SiON also improved the interface quality making the gate stack more thermally stable. The leakage and reliability characteristics for the Poly-Si/AlO/SiON stacks are evaluated and compared with the uncapped Poly-Si/TiN/SiON reference. The AlO capping resulted in two orders of magnitude decrease in leakage at the same capacitance equivalent thickness (CET) compared to the un-capped Poly-Si/TiN/SiON reference. The AlO capping also resulted in improvement lifetime compared to the un-capped Poly-Si/TiN/SiON reference.

In this work we investigate the effect of nitridation on HfSiO's degradation under positive constant voltage stress. A comparison between decoupled plasma nitridation, annealing in NH"3 and no nitridation is made. Stress induced leakage current dominates a wear-out phase before the final hard breakdown, regardless of nitridation. However, this progressive breakdown phase is more pronounced in NH"3 annealed samples resulting in 60 times gate current increase after 10 years, 3 times higher compared to decoupled plasma nitridation and no nitridation. On the other hand, a shorter wear out phase is responsible for faster breakdown in plasma nitrided samples.

MoON has been reported to be a good PMOS candidate. In this paper, we report tuning of the MoON PMOS metal towards Si conduction band-edge with V-T as low as 0.35V for SiON capped with DyO, using a standard high temperature gate first process flow. Consistent shifts of 450mV in V-FB and V-T are observed by capping SiON with DyO for MoON gate. Gate leakage as low as 10(-7) A/cm(2) at 17.6 angstrom EOT is obtained, outperforming HfSiON by 3 orders of magnitude. Intermixing of SiON and DyO is shown to be the key element leading to low EOT and low gate leakage without any degradation of the gate oxide integrity.

Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.

This study investigates the impact of different nitridation processes on hafnium silicon oxynitride (HfSiON) dielectrics. It is demonstrated that the threshold voltage (V-T vs. L-g) behavior at short gate lengths is strongly impacted by the nitridation process, depending on the Hf/(Hf+Si) ratio and the HfSiON thickness. A Plasma nitridation in oxidizing ambient results in a modification of the dielectric that can explain the anomalous V-T behavior in devices integrated with hafnium-based dielectrics and metal gate. Reduction in anomalous V-T behavior and limited gate leakage is achieved by applying a thermal nitridation in a NH3 ambient on Hf-rich silicon oxynitride.

The interaction between the dielectric and the metal gates is crucial for effective workfunction and V"T. In this work, we investigate the effect of a degas step just before the metal gate deposition. The purpose of this step is to remove the water adsorbed at the surface of the dielectric by heating it under vacuum. Removing the water also means the suppression of an O source during following processing steps of the device. This leads to lower oxygen vacancies passivation. When the maximum of water is removed from the surface, NMOS long channel V"T is decreased and PMOS long channel absolute V"T is increased. From the dielectric point of view, degassing leads to lower intrinsic quality as measured by gate leakage increase as a function of the temperature.

The effects of HfSiO nitridation on charge trapping and long-term dielectric reliability are investigated. A comparison between decoupled plasma nitridation, annealing in NH3, and no nitridation is made. It was found that thinner HfSiO layers show less trapped charge. Decoupled plasma nitridation resulted always in a larger hysteresis in the characteristics. A common behavior in all samples was seen at elevated temperatures, which corresponds to lower trapped charge and higher leakage current. Dependence between the trapped charge and the leakage current changes with temperature was established.

We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoOxNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices

The need for nitridation of Hf silicate is controversial. On one hand, it has not been proven that the nitridation is mandatory to have working devices and on the other hand, it is known to increase the charge density. In this paper, we present a detailed comprehensive study of the role and the need for nitridation of Hf-based silicates deposited by Atomic Layer Deposition (ALD). The results are based on a correlation of Fourier-Transformed Infrared Spectroscopy (FT-IR), X-ray Photoelectron Spectroscopy (XPS), High-resolution Transmission Electron Microscopy (HR-TEM) and electrical measurements (gate leakage and mobility). It was observed that the phase segregation in gate dielectrics is not detrimental for the gate leakage density at room temperature. However, the leakage current is significantly increased at higher temperature. The incorporation of nitrogen was either done by NH 3 anneal (at 800C) or by Decoupled Plasma Nitridation (DPN - 25.9kJ). While the DPN or NH 3 anneal prevent phase segregation for 50% Hf silicate, only the NH 3 anneal helps prevent the phase segregation of Hf-rich silicate. Furthermore, the NH 3 anneal increases the interfacial thickness, which produces a very low gate leakage with only 10% loss in mobility at high field. Interestingly, DPN followed by O 2 anneal leads to an advantageous phase segregation of the Hf-rich silicate by transforming the silicate in a HfO 2 /SiO 2 –like stack. As a conclusion, not only the phase segregation of the silicate does not always lead to shorted devices, but it can be beneficial in terms of mobility. However, the phase segregation seems to be responsible for an enlarged trap-assisted conduction mechanism at high temperature. But even if the 50% Hf silicates non-nitrided leads to working devices, the incorporation of nitrogen in the stack improves the Jg/CET trends and is therefore beneficial.