This paper discusses technological choices and resulting performances of an innovative Si/SiGe HBT architecture developed for a new 55-nm BiCMOS platform from STMicroelectronics targeting LEO satellites user terminals application in Ku-Ka bands. Transistor architecture has been designed to combine a low-noise performance with a cost-effective technology (for high-volume production), that are two major requirements for LEO satellite user terminals. Collector integration is widely simplified compared to previous BiCMOS technologies developed by STMicroelectronics taking advantage of ion implantation capabilities. Low-noise performance is addressed by a new generation of emitter-base architecture featuring an epitaxial base link, reducing the base resistance. Record noise performances are demonstrated with $NF_{\text{MIN}}\sim$ 0.6-dB at 20 GHz at device level and 1.13-dB at 11.85 GHz at circuit (packaged receiver) level associated to a gain of ~28dB. SiGe HBT also features −390 GHZ $f_\mathrm{T}$ and −500-GHz $f_\text{MAX}$

RF Front-End Modules (FEM) for both smartphones and infrastructure are today deployed thanks to several technologies (GaAs, GaN, LDMOS, SiGe and RFSOI). RFSOI technology has already completely replaced GaAs for RF switches integration, but due to its very good cost/performances trade-off, RFSOI technology is also a good candidate to enable RF FEM System On Chip (LNA, PA and RF Switch on the same die). We present in this paper the development on 300-mm wafer of a cost-optimized 40-nm PDSOI technology targeting 5G wireless networks from sub-6 GHz up to mmW frequencies. Elementary devices and circuits measurements are reviewed to illustrate achievable performances.

In this paper we present the first integration of a 2D Optical Phased Array (OPA) for 905nm LIDAR applications on our 300mm SWIR photonic platform DAPHNE, based on Si & SiN components.

This paper highlights the optimization of Deep Rib High Speed Phase Modulators for 400G applications thanks to the optimal choice of structure and implants through a Design Of Experiment analysis, including the proposal of a new Deep Rib HSPM with Z-implants. Results show 1,6dB gain in OMA (Optical Modulation of Amplitude) at the same cutoff frequency (fc=[2Pi*RC](-1)) compared to the previous generation [1] with optimized vertical implants, and up to 2,15dB gain vs [1] with the new Z-implant Deep Rib device.

A Silicon photonics platform operating at 100 Gbit/s (53Gbaud-PAM4) per lane is demonstrated. Integration of 60 GHz High-Speed Photodiode and efficient High-Speed Phase Modulator into a 400G-DR4 3D test chip is shown. Extension towards 400G-FR4 is addressed by the introduction of a SiN layer allowing wideband fiber to the chip optical coupling and polarization management.

Silicon photonics technology emerged as a promising solution to address the technical challenges related to 100 Gb/s and 400 Gb/s optical link. Enabling the development of silicon photonics products requires the development of optical passive libraries integrated within conventional CAD tools used in the CMOS design flow. The optimization and modeling of silicon photonics optical passive is therefore a key point that can be addressed by leveraging methodologies that have been previously set up for optimizing RF passive in CMOS and BiCMOS technologies. In this paper, the relevance of such an approach is evaluated: the combination of FDTD electromagnetic simulations and a Design Of Experiments (DOE) prototyping have been used for optimizing scalable Grating Couplers (GCs) targeting Wavelength-Division Multiplexing applications (WDM). The obtained models for the GC have been successfully qualified experimentally.

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

We report results on the fabrication process control and device parameters control of a Silicon Photonics platform using a 300mm industrial fab.

3D integration technology opens the way of heterogeneous silicon platform, as for example, millimeter-wave functionalities could be integrated in future communication modules. Consequently, copper pillar technology realized at 1st level of interconnection between silicon top dies and silicon interposer must be evaluated in this new frequency range. In this paper, a test vehicle has been designed to assess radio frequency behavior of 3D stacking as insertion losses (IL) up to 40 GHz induce by copper pillar interconnection and assembly parameters (pitch, underfilling, …). Copper pillar ground-signal-ground (GSG) vertical transition exhibits IL lower than 0.2 dB at 40 GHz on high resistive silicon substrate and seems to be the minor contributor of all 3D interconnections as TSV, and RDL. Capillary underfill and GSG transition pitch have been evaluated to have a weak impact. Cu ring designed to limit bleed-out and fillet assures PAD integrity and induces a strong signal reflection above 15 GHz. Finally, process assembly robustness of high aspect ratio top die (10 × 3 mm2) has been assessed with DC measurements.

Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above applications at the three typical communication wavelengths and compatible with 3D integration. Main process features and device results are described.

High frequency noise parameters (NF min , R n , B opt and G opt ) determination of Si/SiGe HBTs from STMicroelectronics B5T technology are provided for the first time in the millimeter-wave range. In this paper, an integrated tuner is used for the extraction of high frequencies noise parameters with the multi-impedance method. The designed tuner is composed an active part with a low noise amplifier (LNA) and a passive part with a high performances travelling wave digitally tunable capacitance (DTC), both in series with a transmission line design for phase shifting. Measurements exhibit a state of the art NF min lower than 2 dB at 68 GHz for the HBT.

RF front end module (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passives functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, WLAN and GSM/DCS diplexers have been achieved in a 130 nm SOI CMOS technology. Measured performances (insertion losses ~1dB and isolation greater than 20 dB) are clearly competitive with most commercially available Integrated Device Passive (IPD) solutions.