In this study, we investigated the contact resistance at the interfaces between silicon (Si) and four transition metal silicides (TiSi2, CoSi2, NiSi2, and MoSi2) for various n-type doping concentrations, using ab initio simulations. Transmission spectrum and contact resistance were calculated through density functional theory (DFT) combined with the nonequilibrium Green’s function (NEGF) method, providing atomistic insights into the contact resistance. Two complementary approaches were employed: the valley filtering method, which estimates the theoretical lower limit of contact resistance by comparing the intrinsic transmission modes of Si and silicides, and two-terminal DFT-NEGF calculations on explicit silicide/Si interface structures that incorporate realistic interfacial effects such as Schottky barrier (SB), interface scattering, and metal-induced gap states (MIGSs). TiSi2 and NiSi2 consistently demonstrated the lowest contact resistance due to superior transmission mode alignment with Si, whereas CoSi2 exhibited the highest resistance for all orientations. MoSi2 showed comparable resistance in the (100) and (111) orientations with NiSi2 and TiSi2, but slightly higher resistance in the (110) orientation. These findings suggest that, in addition to TiSi2 and NiSi2, MoSi2 could be a promising contact silicide for advanced technology nodes where minimizing resistance is critical to device performance.

Multilayer two-dimensional (2D) transition-metal dichalcogenides (TMDCs) offer advantages over monolayer (1L), including higher current capability and improved carrier transport. However, direct large-area growth of multilayer TMDCs remains challenging, and most multilayer device studies rely on mechanically exfoliated flakes. Here, we report large-area optimization of multilayer WS2 field-effect transistors (FETs) formed by sequential stacking of CVD-grown monolayer WS2 through combined engineering of the number of channel layers and source/drain contact metals. Thickness-dependent characterization reveals that trilayer (3L) WS2 provides an optimal balance between conduction-path expansion and interlayer transport resistance. Contact engineering further shows that Au electrodes provide superior chemical stability and reduced contact barrier formation. On the basis of these optimized parameters, a large area vertically stacked NMOS inverter was demonstrated using 3L WS2 FETs as the driving transistor and 1L WS2 FETs as the load transistor. The resulting inverter exhibits excellent switching behavior and achieves a record-high voltage gain compared to previously reported complementary FETs (CFETs) and vertically stacked NMOS inverters. This work demonstrates that the combined engineering of the WS2 channel layer number and contact metals enables high-performance vertically stacked inverters and provides a pathway toward scalable, area-efficient three-dimensional integration based on large-area 2D TMDCs.

Spiking neural networks (SNNs) rely on precise spike timing for computation; however, their performance often suffers jitter-induced errors and constraints on synaptic weight updates. In this study, we address this challenge by expanding the neuronal integration window, enhancing temporal robustness while maintaining efficient learning dynamics. We introduce a material-driven approach to expand the operational window of artificial neuron devices, which is defined as the difference between the threshold voltage ( V _th ) and holding voltage ( V _hold ), in ovonic threshold switch (OTS)-based neurons, demonstrating its direct impact on synaptic weight updates and error mitigation. Carbon doping in GeTe-based OTS devices is employed to systematically modulate trap depth variations under an electric field, achieving precise control over V _th and V _hold . Electrical measurements confirm that an optimal 3.4% carbon concentration maximizes the operational window, stabilizing threshold switching and ensuring reliable neuronal operation. To reveal the atomic-scale mechanisms behind this behavior, we perform density functional theory (DFT) simulations, analyzing coordination number and bond angles to elucidate how carbon incorporation modifies trap distributions and influences device characteristics. Finally, we assess the practical impact of operational window expansion by implementing the optimized OTS neurons in a learning framework based on the tempotron learning rule, revealing enhanced spike timing robustness and reduced synaptic weight update constraints. This study provides a scalable pathway toward more reliable spike-based neuromorphic computing to advance the next generation of artificial intelligence hardware.

The atomistic role of C and N co-doping in amorphous GeTe was investigated using a Message Passing Atomic Cluster Expansion-based machine-learned force field and density-functional-theory-based electronic-structure calculations. The machine-learned force field enabled ensemble-level analysis of ten independent amorphous structures for each composition, allowing direct comparison among pristine GeTe, C-doped GeTe, N-doped GeTe, and C/N co-doped GeTe. Structural analyses based on radial distribution functions, coordination statistics, angle distributions, q-parameter distributions, vibrational density of states, and ring statistics reveal that C and N doping preserve the Ge-Te backbone while suppressing Ge-Ge homopolar motifs and introducing dopant-related covalent bonds such as Ge-C, C-C, and Ge-N. These bonding changes shift the Ge-centered local environment away from defective-octahedral-like motifs and toward a more tetrahedral-like, mechanically constrained amorphous network. Electron localization function, bond-motif-resolved inverse participation ratio, and normalized electron-density analyses show that the doped networks exhibit enhanced local electron localization and wider mobility gaps. The representative mobility gap increases from 1.141 eV in pristine GeTe to 1.229 eV in GeTeC, 1.642 eV in GeTeN, and 1.450 eV in GeTeCN. Time-stamped force-bias Monte Carlo simulations at 600 K further show that all doped compositions exhibit reduced atomic displacement compared with pristine GeTe. These results indicate that C and N doping stabilize amorphous GeTe by reorganizing local and medium-range bonding networks, while C/N co-doping produces a non-additive redistribution of structural and electronic characteristics.

As data-centric applications such as AI and network processing grow rapidly, conventional computing systems suffer from performance bottlenecks due to the separation of memory and logic. Ternary content-addressable memory (TCAM) offers a promising memory-centric approach by enabling parallel search operations with three logic states-'0', '1', and 'don't care' ('X')-for enhanced functionality. However, conventional static random access memory (SRAM)-based TCAMs require at least 16 transistors per cell, limiting density and incurring significant power overhead. Here, we present a compact single-transistor TCAM cell based on parallel-channel reconfigurable field-effect transistors (PC RFETs) fabricated using large-area monolayer WSe2. The parallel-channel configuration enables stable ambipolar transport in large-area WSe2, where selective charge-transfer doping with sub-stoichiometric metal oxides converts the homogeneous p-type WSe2 channel into parallel n-type and p-type channels. A tri-layer Al2O3/HfO2/Al2O3 gate stack enables nonvolatile modulation of p-type, n-type, and ambipolar conduction states via gate pulse programming. The PC RFETs demonstrates symmetric conduction (Ion.n/Ion.p ≈ 1.02), high on/off ratios (∼105), and reliable match/mismatch behavior. This RFETs-based a single transistor (1T) TCAM cell is further validated through SPICE simulations. An 1 × 8 array simulation confirms scalability and circuit-level feasibility with a latency of ∼5 ns. This work offers a promising pathway toward high-density and fast operation with compact TCAM for future data-centric computing.

Reconfigurable field-effect transistors (RFETs), which allow postfabrication switching of device polarity, are promising candidates for compact and functionally flexible circuit design. Here, we demonstrate large-scale dual n-/p-channel RFETs based on homogeneous monolayer WSe2, integrated with a charge-trapping layer. Ambipolar transport is achieved by forming parallel n- and p-type conduction paths through selective doping. In addition, a multilayer gate dielectric stack (hBN/HfO2/Al2O3) enables complete nonvolatile switching between n- and p-type modes via charge-trapping. Exploiting this reconfigurability, we realize ternary content-addressable memory using only two RFETs (2T) per cell, where polarity combinations encode the three logic states ('0', '1', and 'X'). Furthermore, a full set of Boolean logic gates─including AND, OR, NAND, and NOR, is demonstrated using series and parallel 2T configurations. These results establish dual n-/p-channel WSe2 RFETs as scalable and functionally versatile building blocks for programmable logic and memory in future computing architectures.

With continued device scaling, the use of copper (Cu) as an interconnect material has reached its limit for two main reasons. First, electron-phonon scattering, which dominates in the bulk form, becomes overshadowed by surface roughness and grain boundary scattering as the dimensions shrink. Second, electromigration becomes increasingly severe under high electric fields, compromising reliability. Each of these degradation factors can be quantitatively evaluated using the figure of merit (FoM) and cohesive energy. In the search for next-generation interconnect materials, Co- and Mo-based binary alloys were investigated using density functional theory (DFT) calculations combined with Boltzmann transport theory. The directionally averaged FoM and cohesive energy were computed as indicators of size-dependent resistivity and electromigration resistance, respectively. By applying screening criteria-cohesive energy greater than 5.5 eV per atom and FoM less than 6.70 & times; 10-16 Omega m2 (the FoM of Cu)-four promising Co-based alloys and seven Mo-based alloys were identified. These results highlight the strong potential of Co- and Mo-based binary alloys for future interconnect applications. Furthermore, similarities in Fermi surfaces, coupled with the FoM analysis, validate these alloys as suitable candidates for advanced interconnect technologies.

Here, we demonstrate an interface-controlled, self-rectifying resistive switching memory integrated in a 4K (64 × 64) crossbar array (CA). A simple Ru/HfAlOx/TiN stack composed of fabrication-friendly materials enables both nonvolatile resistive switching and polarity-dependent rectification. The interface-controlled operation suppresses the stochastic variability typically observed in conventional resistive switching memories and removes the need for electroforming, which is advantageous for mass production. In the 4K crossbar array, we achieve 100% functional yield without operational failure and experimentally verify analogue vector-matrix multiplication (VMM). The same interface-controlled switching yields analogue-like conductance updates with linear and symmetric modulation, and we present inference simulation results based on the measured characteristics. Finally, current-conduction fitting and drive-level capacitance profiling (DLCP), together with atomistic numerical simulations, elucidate a switching mechanism governed by the motion of internal mobile charges at the interfaces.

In this work, we propose silicon (Si) CMOS-compatible ternary logic technology. Our Si ternary-CMOS (T-CMOS) is simply realized by introducing additional drain resistance, which limits the on-current to a gate-independent constant level current, thereby enabling a third logic state in the voltage transfer curve. TCAD simulations calibrated to experimental data of planar MOSFETs, FinFETs, and GAAFETs confirm stable ternary operation with low static power consumption and short delay. Notably, GAAFETs-based T-CMOS achieves superior current scalability and a large static noise margin, while supporting both binary and ternary logic operations depending on the supply voltage.

This work investigates the effect of quantum confinement (QC) on the performance of FinFETs and nanosheet FETs (NSFETs) with industry standard <110> transport direction on (100) silicon wafers, using three-dimensional semi-classical Monte Carlo simulation with quantum corrections. Due to different QC directions, NSFETs, unlike FinFETs, exhibit greater occupation of valleys with lower transport effective mass. Furthermore, QC effects, which increase phonon and surface roughness scatterings, are relatively less detrimental in NSFETs as the lowest energy valleys in NSFETs have relatively larger QC effective mass. Consequently, NSFETs deliver higher drive current than FinFETs of the same channel cross-section. The influence of gate length and channel thickness also is analyzed, with optimal performance achieved at a gate length of 15-17 nm and channel thickness of 4-4.5 nm. These results highlight the critical role of QC in nanoscale device behavior and demonstrate the advantage of NSFETs for future technology nodes.

We propose a silicon (Si) CMOS-compatible ternary logic (T-CMOS) technology achieved by a simple modification of conventional MOSFETs. By introducing an additional drain resistance, the on-current is limited to a gate-independent constant level, thereby enabling a stable third logic state in the voltage transfer curve (VTC). TCAD simulations calibrated to experimental transfer characteristics of planar FETs and GAAFETs confirm robust ternary operation with low static power consumption and short propagation delay. Among the devices, GAAFET-based T-CMOS achieves the most favorable performance, demonstrating superior current scalability and a large static noise margin (SNM) of 149 mV/dec at VDD = 0.7 V. Furthermore, the circuit supports hybrid operation, switching between ternary and binary logic depending on the supply voltage.

In this study, we propose ferroelectric-based reconfigurable field-effect transistors (FeRFETs) that utilizes the structure of a fully depleted silicon-on-insulator field-effect transistors (FDSOI FETs). In FeRFETs, the non-volatile and reconfigurable electrostatic doping facilitated by ferroelectric enables type conversion. Through the TCAD simulations calibrated with the experimental data, we confirm a reconfigurable high doping level (>1 x 1021 cm(-3)), a clear type conversion and highly tunable performance in FeRFETs. It is also found that carefully tailoring coercive field (E-c) is important to maximize the performance of FeRFETs.

2D materials have emerged as promising candidates for next-generation field-effect transistors (FETs) owing to the atomically thin geometry and excellent electrostatic gate control. Here, double-gate vertical sidewall FETs based on chemical vapor deposition-grown monolayer WS2 are demonstrated and, for the first time, report vertical multi-channel nanosheet FETs (NSFETs). By implementing a dual-step sidewall profile, steep SiO2 surfaces are obtained, which enabled seamless WS2 adhesion and contributed to enhanced device yield. The fabricated vertical sidewall WS2 FETs exhibited good subthreshold swing (SS) and effectively suppressed short-channel effects at channel length as short as 150 nm. Logic gates including inverters, NAND, NOR, AND, OR, and SRAM are integrated using vertical sidewall and planar WS2 FETs, validating the feasibility of area-efficient integrated circuit. Furthermore, improved drive current is achieved in vertical multi-channel NSFETs realized by stacking WS2 channels and employing a gate-all-around-like structure. These results highlight the potential of vertical sidewall FETs for enabling area-efficient, ultra-dense integrated circuits.

MoS2, one of the most researched two-dimensional semiconductor materials, has great potential as the channel material in dynamic random-access memory (DRAM) due to the low leakage current inherited from the atomically thin thickness, high band gap, and heavy effective mass. In this work, we fabricate one-transistor-one-capacitor (1T1C) DRAM using chemical vapor deposition (CVD)-grown monolayer (ML) MoS2 in large area and confirm the ultralow leakage current of approximately 10(-18) A/mu m, significantly lower than the previous report (10(-15) A/mu m) in two-transistor-zero-capacitor (2T0C) DRAM based on a few-layer MoS2 flake. Through rigorous analysis of leakage current considering thermionic emission, tunneling at the source/drain, Shockley-Read-Hall recombination, and trap-assisted tunneling (TAT) current, the TAT current is identified as the primary source of leakage current. These findings highlight the potential of CVD-grown ML MoS2 to extend the retention time in DRAM and provide a deep understanding of the leakage current sources in MoS2 1T1C DRAM for further optimization to minimize the leakage current.

Transport characteristics of two-dimensional (2D) materials such as MoS2 and InSe exhibit strong dependence on the thickness, yet the detailed theoretical understanding remains incomplete. Here, we investigate intrinsic layer number -dependent electron transport properties by employing a combined first-principles and semi-classical full-band Monte-Carlo (SCMC) simulation framework. Electronic band structures and phonon-limited scattering rates are obtained from density functional theory (DFT) and density functional perturbation theory (DFPT), and subsequently incorporated into SCMC carrier transport simulations. For MoS2, mobility remains nearly unchanged from monolayer to bilayer, but decreases significantly in trilayer due to enhanced intervalley scattering into low-mobility Q-valleys. Meanwhile, InSe exhibits a monotonic increase in mobility with increasing thickness, attributed to the reduced density of states and suppressed scattering. Despite a moderate reduction in saturation velocity at high electric fields, InSe consistently outperforms MoS2 in terms of mobility. Valley-resolved drift velocities and populations are analyzed to elucidate the layer number-dependent behaviors of mobility and velocity saturation.

The structural and transport properties of CoTi binary alloys were investigated using density functional theory (DFT) calculations to evaluate the potential as a single-layer liner/barrier in liner-less Co interconnects. Cohesive energies of CoTi binary phases were calculated to identify thermodynamically stable compositions, with CoTi, Co2Ti, and Co3Ti exhibiting the lowest values. Interface binding energies were then evaluated for multiple Co/CoxTiy configurations and compared with conventional Cu/TaN interfaces. We identified several Co/CoxTiy interfaces with binding energies lower than similar to-5 J/m(2) such as fcc-Co(100)/CoTi(110), which exceeds that of the conventional Cu(111)/TaN(0001) interface. Finally, electron transport across the via stack was analyzed. Co/CoxTiy/Co via structures showed consistently higher specific conductance compared to Cu/TaN/Ta/Cu, with the highest value of 4.40 x 10(-4) S/nm(2) observed for fcc-Co(110)/Co2Ti(110)/ fcc-Co(110). These results support the use of CoTi alloys as reliable, high-performance alternatives to conventional liner/diffusion barrier stacks in future interconnect technologies.

The restorative effects of sulfur (S)-passivation through low-temperature (160 °C) post-S annealing on the performance and stability of monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) are investigated. S-passivation suppresses S vacancies in the monolayer MoS2 channel, restoring its intrinsic electrical and material properties and leading to enhancements in field-effect mobility from 8 to 95 cm-2 V-1 s-1 and subthreshold swing from 0.21 to 0.10 V dec-1. Hole-trapping associated with S vacancies results in the instability of the MoS2 FETs under a negative bias stress, whereas S interstitials acting as electron trap states contribute to the instability of the S-passivated MoS2 FETs under a positive bias stress. The effects of S-vacancy suppression on the charge-transport properties of the MoS2 FETs are assessed by analyzing their activation energies and densities of states based on the reduction in defect states by S-passivation. An N-channel metal-oxide semiconductor inverter consisting of the S-passivated MoS2 FETs exhibiting improved voltage gains is demonstrated for the first time, indicating its potential application in logic circuits based on monolayer transition-metal dichalcogenides.

Neuromorphic computing has emerged as a promising strategy for overcoming the von Neumann bottleneck by enabling energy-efficient parallel information processing. To realize such systems, it is crucial to develop artificial synaptic devices that are both energy-efficient and highly scalable. In this study, we present a single-layer MoS2-based synaptic field-effect transistor (FET) with a high-kappa top-gate dielectric stack for low-power, nonvolatile synaptic operations. The absence of a blocking layer simplifies the fabrication process while maintaining reliable memory characteristics. Synaptic weights are effectively modulated through the trapping and detrapping of electrons within a HfO2 layer. The device exhibited stable long-term potentiation (LTP) and depression (LTD) with excellent endurance and reproducibility. Furthermore, the experimentally measured synaptic characteristics were implemented in a software-based deep neural network, achieving a recognition accuracy of 95.9% on the MNIST handwritten digit classification task. These findings highlight the potential of single-layer MoS2 synaptic transistors as scalable energy-efficient neuromorphic building blocks.