The objective of this work is to briefly illustrate the breadth of problems industrial technology computer aided design (TCAD) departments are expected to address when supporting modern semiconductor process development, focusing on two important trends. The first is the incredible expansion of the simulation domain both downward to atomic dimensions and upward to the very large-scale die-level simulations needed for product design. The second trend is the continuing necessity of using computational efficient continuum approaches, fortified with more physically rigorous methods, to meet both accuracy and wall-clock time requirements of industrial process development. Both of these trends will be illustrated with applications work done at Intel.

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems.

Solid Phase Epitaxial Regrowth (SPER) is of great technological importance in semiconductor device fabrication. A better understanding and accurately modeling of its behavior are vital to the design of fabrication processes and the improvement of the device performance. In this paper, SPER was modeled by Molecular Dynamics (MD) with Tersoff potential. Extensive MD simulations were conducted to study the dependence of SPER rate on growth orientation and uniaxial stress. The results were compared with experimental data. It was concluded that MD with Tersoff potential can qualitively describe the SPER process. For a more quantitatively accurate model, a better interatomic potential are needed.

TCAD process and device simulation has been used to understand and optimize advanced logic devices for many technology nodes. Stress engineering and modeling has also been an important part of device analysis for decades, long before it was intentionally engineered for transistor performance. Initial stress studies were process-only simulations of stress-dependent silicon oxide growth for isolation [1,2,3,4,5] and were extended to include strain from thermal mismatch, intrinsic, and dopant strain [6,7]. Process and device simulations have also been used to explain increased junction leakage [8] and layout dependent reduced electron mobility [9]. The first intentionally engineered strain sources include nitride capping layers and embedded SiGe S/Ds [10,11]. As technology development has progressed, both the unintentional and engineered strain sources have changed considerably. Device scaling modifies the geometry, which in turn changes the stress from generation to generation. In addition, new technology features and architectures can affect both intentional and unintentional strain sources. This paper reviews how strain sources have changed, how modeling has evolved to simulate the effects of strain in advanced logic devices, and the outlook for engineering strain in future device options. To model stressed devices, both front end process models and stress dependent mobility device models have been developed [12,13]. To evaluate stress effects on device performance requires a process simulator for structure creation, stress and dopant diffusion/activation modeling, and a device simulator that accurately captures the resulting electrostatics as well as carrier mobility and external resistance. In this work, process simulation is performed using an internally modified version of FLOOPS [12,14,15,16,21], while drift diffusion simulations are run with MDS [17] which includes models for stress, orientation and ballisticity on transport [13,18,19,20,22]. The first engineered stress in NMOS employed tensile nitride films over the polysilicon gate [10,11,12,13]. At the 45nm node, HiK and metal gates were introduced, removing the nitride induced stress, but allowing for other strain sources including tensile contact metals and compressive gate metals [23]. In addition, the strain due to edge dislocations in lattice improved NMOS device performance [16]. When trigate transistors were introduced at the 22nm node [24], the strains changed again. From the modeling perspective, trigate devices necessitated both routine 3D simulation [21] and capturing transport in [110] confined channels which changes the mobility response to stress [25]. Poor epitaxial regrowth in the trigate architecture removed edge dislocations as a strain source but allowed for stress from tensile gate metals and also a novel ILD0 [26]. Figure 1 shows stress simulations for different NMOS devices. The main engineered strain source for PMOS devices is embedded SiGe S/Ds. Over time, the Ge fraction was increased while the distance from the SiGe S/D to the channel was decreased [10,11,12,13,17]. In the 45 nm technology node [23], removal of the polysilicon gates increased channel compression [17]. The introduction of trigate devices [24] resulted in the need to capture stress effects on transport in [110]/(110) channels, which has a higher hole mobility but less stress response. Initially there was a concern that the strain from epi S/Ds growth would not be maintained in trigate devices,; however, its effectiveness was later confirmed with TEM measurements [27]. Modeling both edge dislocations [16] and Ge profiles in S/D are important for matching measured strain. Figure 2 shows stress profiles for different PMOS devices. Stress from SiGe S/Ds were also found to exhibit layout effects [28]. This requires simulating stress in an area larger than the device to accurately capture the resulting stress in the channel. Capturing unintentional strain sources, which can easily be overlooked, also makes simulating a larger area critical. For example, ILD0 and gate cut fill strain [29], which occur outside the diffusion box, impact device performance. Future logic device options will involve new materials and architectures which impact device responses to stress and present novel opportunities to engineer strain. New channel materials include sSi for NMOS, sSiGe for PMOS [30], and Ge for NMOS and PMOS [31,32]. Process flow concerns will also evolve, i.e. devices engineered with stress from the substrate will have challenges maintaining stress throughout an epi S/D process and the stress will depend on fin length. Future device architectures include nanowire/nanosheets [33], forksheets [34] and device stacking, which will allow mixing and matching both materials and architectures; examples include combining Ge PMOS nanosheets and Si NMOS finfets [35]. A stress simulation of tensile gate metal for the stacking approach in reference [35] is shown in Figure 3 and illustrates how the same strain source results in different stresses depending on architecture. Figure 1

During the past decade, significant progress has been achieved in the application of material modeling to aid technology development in semiconductor manufacturing companies such as Intel. In this paper, we review examples of applications involving a complex set of material modeling tools and methodologies and share our perspective of the future of the area. Examples are given illustrating the landscape of useful physical models and approaches along with commentary addressing tool relevance and simulation efficiency issues. While the scope of this paper precludes providing in-depth details, references to more focused publications are shared. Finally, we outline how to approach constructing a general infrastructure for supporting TCAD material modeling applications.

The metal-semiconductor contact resistivity has started to play a critical role for the overall device performance as Si is reaching 10-nm size ranges. The International Technology Roadmap for Semiconductors (ITRS) target predicts a requirement of 10(-9) Omega.cm(2) by 2023 which has been a challenging target to achieve. This paper explores the impact of doping concentration, Schottky barrier height, strain, and SiGemole fraction on the resistivity of Si/SiGe p-type metal-oxide semiconductor (PMOS) contacts with 20-band atomistic tight binding quantum transport simulations. Commonly used simple effective mass approximation models are shown to overestimate the resistivity values. The predicted model results are compared with experimental data and the device parameters needed to achieve 10(-9) Omega.cm(2) are identified.

Adherence to Moore's law is arguably the key technological and economic driver for the nanoelectronics industry. Geometric transistor scaling enabled process manufacturing technology to keep pace with Moore's law until the early 2000s, when it was realized that disruptive enhancements beyond geometric scaling would need to be implemented. One key innovation was the introduction of strain enhancements into the transistor architecture. This development necessitated the requirement for the measurement of transistor strain and also the characterization of various stressor systems. This chapter reviews the fundamental aspects of strain with transistor device performance and the key analytical developments that have filled this critical capability gap. Various analytical methods are reviewed, each with unique strengths in providing a range of capabilities that include fundamental characterization, rapid analysis, and measurements at the device, die, and wafer levels. We also examine the scalability and versatility of these analytical methods as they will be needed to provide a path for future strain engineering programs with a new class of emerging transistor material and architectural options.

With continuous shrinking of devices in accordance with Moore's law, metal-semiconductor resistivity starts playing an important role for device performance. To meet ITRS target of 10 -9 Ω·cm 2 by 2023, it is important to evaluate the effect of different device parameters such as doping concentration, Schottky barrier height, strain and SiGe mole fraction on contact resistivity. In this work, such a resistivity study has been done on Si/SiGe PMOS contacts through 10-band atomistic tight binding quantum transport simulations. Optimum target values for barrier height as a function of doping concentration are obtained.

Device modeling has been essential in discovery of innovative concepts, assessing their value proposition and in guiding the process engineering of devices to continue Moore's Law performance scaling for Metal Oxide Semiconductor Field Effect transistors (MOSFET) [1]. TCAD has traditionally relied on continuum model of transport by solving drift-diffusion (DD) equations and including band structures through effective mass descriptions. These approaches break in nanometer scale quantum devices. Higher level models of quantum transport atomistic nonequilibrium Green's function (NEGF) [2] and semiclassical Monte Carlo (MC) [3] simulations are used for assessing new materials and novel concept devices. NEGF device simulations typically do not include realistic structures and assume a simplified form of scattering. Monte-Carlo simulations account for quantum effects, for example, the source-drain tunneling, within effective quantum correction potential approaches. The corrections to the drift-diffusion model through ballistic mobility models [4] [5] and quantum corrections [6] have been used to extend TCAD simulations to scaled devices. In this talk we will use the tool box of these simulation methods to discuss various important aspects of physics in scaled devices and their impact on assessing new materials as alternative channels using TCAD modeling. We will discuss the distribution of resistance at low and high supply voltage in short devices which approach ballistic limit and discuss the implication it has on assessing advantage of Ge vs Si channel on-current performance of PMOSFET. Scaling device crossection size down to a few nanometers brings us to a modeling realm where we can count the number of atoms in a device. In this realm we typically rely on tight-binding atomistic models to capture effects of confinement in devices [2]. We will discuss the dependence of bandgaps on size of the nanowire and ultra-thin body in III-V, Si and Ge materials. Tight-binding atomistic descriptions meet their set of challenges in modeling ultra-scaled devices where the effects of interfaces and imperfections become critical to account for. We will show that using known bulk tight-binding parameters for each material alone cannot in general describe even ideal interfaces between semiconductors. We will discuss this on the example of InAs hydrostatically strained to Si interface. This brings us to use more advanced Hamiltonians, such as, for example, Extended Huckel Theory (EHT) [7], and have a close coupling between tight-binding models and ab-initio Density Functional Theory (DFT) methods. We will apply the Extended Huckel theory to model the bandstructures of bulk semiconductors and nanowires. We will show that the Huckel method is predictive in modeling the effect of confinement in nanowires. We conclude with a discussion of challenges of bridging the gap between detailed material modeling and characterization and semi-classical device level modeling.

Front end process simulation is an invaluable tool in assessing current and future process options. This review describes the application of process simulation in modeling geometry, doping and stress effects in advanced logic processes. Continuum and atomistic approaches, both necessary to capture the physics involved with the most advanced options, are discussed. Also detailed are advancements in numerical techniques which enable the efficient and robust simulation necessary to keep pace with technology development.