The device performance of silicon nanotube field effect transistor (Si-NT-FET) having tubular channel and controllable by an inner and outer gates is presented. The inner and outer gates render effective charge control inside the channel providing the Si-NT-FETs excellent immunity to short channel effects. Evaluations of electrical performances of Si-NT-FET using well calibrated 3D device simulations show that Si-NT-FETs can outperform Si-nanowire (NW)-FETs in terms of drive currents and SCEs. Our evaluation further shows that Si-NT-FETs can provide ~2× higher drive current compared to Si-NT-FET of the same diameter. This excellent electrical performance makes Si-NT-FETs promising candidates to extend CMOS scaling roadmap beyond Si-NW-FET.

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing t...

A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizing the one-dimensional (1-D) transmission line model to 2-D and 3-D with appropriate boundary conditions. The model is compared with the S/D resistance determined from 3-D device simulations and experimental data. We show excellent agreement between our model, the simulations, and experimental data.

For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mu m(2). Record NMOS/PMOS drive currents of 1000/575 mu A/mu m, respectively, have been achieved at 1 nA/mu m off-current and 1.1V V-dd with a low cost process. With this high performance transistor, V-dd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L-gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel work-functions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge.

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C-sub) epitaxial Si:C and laser spike annealing (LSA) for increased C-sub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C-sub and 60% Rch reduction for 2.2% C-sub are demonstrated.

Using PMOSFETs with a range of built-in process induced stress and four-point bending characterization, we present evidence that the stress response of PMOSFETs increases with channel stress. A novel method incorporating the characterization data with channel stress simulation has been developed which shows excellent agreement between our prediction and measured transistor performance data for nitride etch stop layer splits. Our analysis indicates that PMOSFETs will continue to show increasingly effective performance enhancement at higher channel stress

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Optimization of post nitridation annealing (PNA) in plasma nitrided gate oxide integration exhibited reduction of gate leakage current and improvement of negative bias temperature instability (NBTI) without drive current loss have been demonstrated. An improved interface quality by a high temperature or a high pressure O 2 PNA is the main factor to improve channel mobility. The addition of both post clean annealing (PCA) and post oxidation annealing (POA) allows for gate dielectric scaling down with the benefit of drive current improvement. An increase in oxide thickness and a decrease in relative nitrogen concentration resulted in the improvement of NBTI characteristics.

First functional 45nm SGOI CMOS devices on bonded SGOI substrates with T-SOI<45nm exhibited superior short-channel control and comparable reliability to SOI devices. A 67% Gm enhancement was observed in long-channel nMOS SGOI devices, 18% drive current increase for short-channel SGOI devices, and 12% faster ring-oscillators were exhibited with respect to control SOI devices. Functional SRAM bit cells down to V-dd = 0.9V were also demonstrated.

By utilizing the current transients in scanning tunneling spectroscopy, the local interfacial electronics between multiwalled carbon nanotubes and several supporting substrates has been investigated. Voltage offsets in the tunneling spectra are directly correlated with the formation of a dipole layer at the nanotube-substrate interface, strongly suggesting the formation of interface states. Further, a systematic variation in this local potential, as a function of tube diameter, is observed for both metallic substrates (Au) and semimetallic substrates (graphite). In both cases, for tubes with diameters between similar to5 nm and 30 nm, the interfacial potential is nearly constant as a function of tube diameter. However, for tube diameters <5 nm, a dramatic change in the local potential is observed. Using ab initio techniques, this diameter-dependent electronic interaction is shown to derive from changes in the tube-substrate hybridization that results from the curvature of the nanotubes.

Since the discovery of carbon nanotubes in 1991 [1], researchers have envisaged potential applications such as nanoscale electronic circuits and the construction of complex carbon-based nano-machines. Thus, the assembly of basic building blocks of complex nano-architectures, such as conjugated polymers and nanotubes, has been a driving goal of much of the nano-science community. A first step towards realizing this goal may be the attachment to, or modification by carbon nanotubes of structures such as polymers. This leads to the possibility of assembling individual polymer molecules onto carbon nanotubes with the net effect being the modification of the polymer's electronic properties and structure in a predictable way. To accomplish this, clearly, a more detailed understanding of the interactions between conjugated polymers and carbon nanotubes must be sought. In this paper, we describe the assembly of the polymer, poly(m-phenylenevinylene-co-2,5-dioctoxy-p-phenylenevinylene) (PmPV), into a coating around single-walled carbon nanotubes. Using scanning tunnelling microscopy, and scanning tunnelling spectroscopy, we demonstrate that the low-energy electronic structure of the assembled material is dominated by the one-dimensional nature of the nanotube as reflected in van Hove singularities. Further, we examine the modifications to electronic structure at higher energies using spectroscopy, which suggests that the polymer's electronic structure is altered by the introduction of nanotubes.

By utilizing the current transients in scanning tunneling spectroscopy, the local interfacial electronics between multiwalled carbon nanotubes and several supporting substrates has been investigated. Voltage offsets in the tunneling spectra are directly correlated with the formation of a dipole layer at the nanotube-substrate interface strongly suggesting the formation of interface states. Further, a systematic variation in this local potential, as a function of tube diameter, is observed for both metallic substrates (Au) and semi-metallic substrates (graphite). In both cases, tubes with diameters between ~ 5 nm and 30 nm, the interfacial potential is nearly constant as a function of tube diameter. However, for tube diameters < 5 nm, a dramatic change in the local potential is observed. Using ab initio techniques, this diameter dependent electronic interaction is shown to derive from changes in the tube-substrate hybridization that results from the curvature of the nanotubes.

Nitrogen doped carbon nanotubes have been synthesized using pyrolysis and characterized by Scanning Tunneling Spectroscopy and transmission electron microscopy. The doped nanotubes are all metallic and exhibit strong electron donor states near the Fermi level. Using tight-binding and ab initio calculations, we observe that pyridine-like N structures are responsible for the metallic behavior and the prominent features near the Fermi level. These electron rich structures are the first example of n-type nanotubes, which could pave the way to real molecular hetero-junction devices.

We have studied the effect of strain on the electronic properties of multiwall carbon nanotubes using scanning tunneling microscopy and spectroscopy. While small elastic strain causes no change of the electronic properties of the nanotubes, tubes under large strain by lying over an inter-grain boundary of the Au substrate show drastic electronic heterogeneity. The observed variation in local electronic property is explained in terms of the mechanical relaxation of the outer most layer of the tube. This provides first evidence of the effect of mechanical modification on local electronic structure of a carbon nanotube.

We report the use of high power ultrasonic agitation to create inelastic deformations in multiwalled carbon nanotubes. Using STM coupled with TEM we show that this damage can range from kinking to breaking of continuous tube walls into segments. Such deformed tubes provide an insight into the role of re-hybridization in the electrical and mechanical properties of tubes.