This simulation work studies whether band-to-band-tunneling leakage in short-channel germanium FinFETs and nanowires can be mitigated by the band gap widening resulting from quantum confinement. Through a combination of drift-diffusion and coupled Poisson-Schrödinger simulations, two possible solutions are investigated: can the BTBT rate be lowered sufficiently? Secondly, can the tunnel path be cut off by band gap widening? Our results indicate that by exploiting the band gap widening in narrow devices, gate-induced drain leakage due to band-to-band tunneling in Ge FinFETs and nanowires can meet the high-performance and low operating power off-state leakage specifications of CMOS technology. However, the low standby power off-state target seems out of reach.

This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

To summarize, this paper explores key challenges of FinFET stress engineering that is based on the epitaxial SiGe S/D. These challenges are FinFET-specific and can be addressed by carefully balancing several design and process trade-offs simultaneously. An appropriate 3D modeling methodology is demonstrated to handle the new FinFET-specific design and process challenges.

Since the advent of computer modeling of semiconductor processes and devices in the 1970s, Technology Computer-Aided Design (TCAD) has been an integral part of technology development over the past four decades. Today, the use of TCAD has become widespread not only for “More Moore,” but also “More Than Moore” technologies (Fig. 1). As process and device complexity continues to rise, so does the complexity in technology modeling. This paper discusses the present state and future challenges of front-end process and device modeling.

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

Recessed Si/sub 0.8/Ge/sub 0.2/ source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drive-current improvement from recessed Si/sub 0.8/Ge/sub 0.2/ plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L-s/d) and the device width are further scaled.TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman Spectroscopy (muRS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

This paper discusses different aspects of modeling the impact of stress on silicon processes and devices. The models account for the stresses due to the thermal mismatch during the temperature ramps, volume expansion and shrinkage, lattice mismatch stress due to the material composition and impurities in the lattice. It is important to simulate the evolution of the stresses coming from different sources in order to determine total stress distribution during the process flow. The peak stresses generated during the process steps might create extended defects, while the residual stresses at the end of the process flow determine the electrical performance of the device.

Analog superconductive components have been integrated to form a device capable of cross-correlation between wideband analog input signals. The device contains a tapped niobium delay line, tunnel-junction mixers, a lumped-element L-C resonator, and a tunnel-junction comparator. The tapped delay line is realized by a niobium stripline folded in a meander pattern on a rectangular silicon substrate. An array of Nb/Nb2O5/Pb tunnel junctions acts as a mixer to form the product of delayed samples of two carrier-offset analog signals counterpropagating along the transmission line. The resultant mixer products from the junction arrays are integrated and stored in a high-Q (≈ 600) resonator consisting of a lumped-element L-C network, tuned to the offset frequency. The low-leakage capacitor dielectric is formed from electrolytically anodized niobium. A superconductive tunnel junction imbedded in the resonator circuit is operated as a variable-threshold comparator to detect the time-integrated current stored in the resonator. Performance results from such a time-integrating correlator are presented, along with a discussion of the important design issues as they relate to analog signal processing.

We report on further studies of the effects of hydrogenation of sputtered amorphous silicon barriers upon the current-voltage (I-Y) characteristics of Nb-Nb Josephson tunnel junctions. For composite trilayer barriers (a-Si/a-Si:H/a-Si) which are deposited using 8 mT of Ar, we find that there is an abrupt improvement in device chararteristics when the central hydrogenated layer is deposited using a hydrogen partial pressure which exceeds about 0.5 mT. We attribute this to the reduction in the density of localized states in the a-Si:H layer. We have observed excellent I-Y characterisitics with trilayer barrier devices whose central hydrogenated layer is only about 1/7 of the thickness of the entire barrier. This observation suggests that localized states near the geometric center of the barrier are the most significant in degrading device characteristics. Annealing experiments and published data on the diffusion of deuterium in a-Si suggest that the composite barriers will be extremely stable during processing and storage. Zero bias anomalies in device I-Y characteristics and spin density in the a-Si and a-Si:H layers have been measured. Suggestions for future experiments are made.

We describe a technique for fabricating magnetically coupled Josephson logic and memory circuits and SQUIDs which uses only two superconducting layers. These two layers perform multiple functions as the base and counterelectrodes of the tunnel junctions, the SQUID inductance and control lines, and the signal lines and groundplane between gates. This technique is illustrated by the specific example of a two junction, resistively damped SQUID designed to be fabricated using an all-refractory process which employs a total of five masking levels.

High quality Josephson tunnel junctions have been fabricated whose tunneling barrier is polycrystalline germanium chemically vapor deposited on a NbN base electrode and covered by a Nb counterelectrode. These junctions have excellent characteristics for device applications: values of Vm (the product of the critical current and the subgap resistance measured at 2 mV and 4.2 K) ranging between 35–48 mV, ideal threshold curves, a steep current rise at the gap voltage, and Josephson current densities from 100 to 1100 A/cm2.

A process for the fabrication of Josephson integrated circuits is described which uses only refractory materials. The Josephson devices are Nb-Si-Nb tunnel junctions which are formed in the initial phase of the process. After depositing a Nb-Si-Nb `trilayer' over the entire substrate, the individual devices are isolated by the selective niobium anodization process (SNAP). Other materials used are molybdenum for the normal resistors and bias-sputtered SiO/SUB 2/ for additional insulator layers. The process uses only five photolithographic steps to produce circuits of the direct-coupled isolation type. This simplicity is achieved by using some layers for multiple purposes and by fabricating components with different functional purposes in a single step. For example, the lower electrode of the Josephson devices also functions as the ground plane and the contacts to the ground plane are actually large-area Josephson junctions formed simultaneously with the active devices. Low capacitance junctions (~0.025 pF//spl mu/m/SUP 2/) are produced with good uniformity.

We have compared the tunneling characteristics of Nb-Si-Nb junctions whose amorphous silicon barriers have been sputtered in pure Ar with those sputtered Ar-H2plasmas as well as in various combinations. We observe lower subgap currents with composite barriers which comprise a central region which is hydrogenated but which is sandwiched between two thin unhydrogenated layers. The improved tunneling characteristics may be associated with the lower density of localized states in the hydrogenated silicon.

We have examined the suitability of Nb-aSi-Nb tunnel junctions, patterned by the selective niobium anodization process (SNAP), for large scale integrated circuit applications. Using sputtered SiO2as the SNAP anodization mask, the device area closely reproduces the mask area, with undercut < 50 nm, and no detectable perimeter effects. The critical current density increases with the radial distance from the center of the Si target, due to the quadratic decrease in the thickness of the sputtered Si barrier: at a distance of 1 cm, this increase is ∼ 10%. Arrays of 12 μm × 12 μm junctions have been fabricated with standard deviations of the critical current of ∼ 1%. These arrays have been thermally cycled between room temperature and 4.2 K over 600 times without change. Junctions can be annealed at 175°C for extended periods of time to increase the current density by up to ∼ 50% with no deterioration in junction quality.

We describe a Josephson integrated circuit technology based on Nb-aSi-Nb tunnel junctions patterned by the selective niobium anodization process (SNAP). This technology also uses Mo resistors, bias-sputtered SiO2insulators, and Nb wiring to complete circuits of the direct current-injection variety using only five photolithographic steps. We have fabricated and tested chains of JAWS "OR" gates produced with this process. Proper operation is obtained for supply and offset currents varying by ± 20% (FANOUT = 1) and ± 10% (FANOUT = 2). This is in good agreement with calculations.

: This program is part of an ongoing effort to fabricate all-refractory S-I-S devices for use as mm-wave detectors and mixers in the quantum regime, and operating in the temperature range of 8-10 K. There are four ongoing approaches to achieve this goal: (1) Development of high-quality NbN-barrier-Nb S-I-S junctions as an intermediate goal towards fabricating all-NbN junctions; (2) Actual development of all-NbN junctions using the results of (1) above as a guide; (3) Development of an in-house NbN deposition capability in order to speed the progress on (2) above; and (4) The use of existing all-NB digital circuit fabrication capability to design and fabricate mm-wave mixers to operate at T less than or approx. 4.2 K, thus gaining valuable experience that can be applied to the eventual design of all-NbN mixers. Sputtered NbN-a:Si-NB Josephson tunnel junctions fabricated using SRC's SNAP process (Selective Niobium Anodization Process) have been developed. All-NbN devices using the plain a:Si barrier have been developed to the point where they exhibit S-I-S tunnelling characteristics. Fourteen types of mm-wave mixer chips have been designed in collaboration with the Goddard Institute for Space Studies using the existing all -NB digital circuit fabrication process. Masks were fabricated, and a trial fabrication proved the integrity of the process. The viability of the proposed mounting scheme has been experimentally ascertained.