For sub-10nm technology generations, the conventional scaling strategy, viz. simply decreasing poly pitch (PP) and metal pitch (MP) , does no longer bring sufficient area reduction to maintain Moore’s Law [1]. To continue the scaling rat race, standard-cell library designers are now implementing innovative library-cell concepts (referred to as scaling boosters ) that provide additional area, performance, and power (APP) benefits and help justifying the financial investments for the next technology node [1]. This concept is known as design-technology co-optimization (DTCO).

We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with backside metals and buried power rail. Two different options for the backside to frontside connectivity are included: μTSVs and nTSVs (respectively 0.5μm, 0.09μm diameter and 1Ω, 10Ω nominal resistance). Further, Hybrid Bonding CuPads are used to deliver power to the second die in the stack. A commercial power analysis tool is extended to support both the TSV and the pads structures, to tackle both inter-die and on-die power delivery challenges. A L1 cache memory implemented on the top of a core is used as test case to assess the performance of the proposed metal stack. A 69% reduction in average static IR-drop is observed with the BS-PDN compared to the conventional frontside. Further, 81% and 77% average and peak IR-drop reductions are obtained with nTSV compared to μTSV.

A new device architecture such as Forksheet emerges a promising candidate to the extension to Nanosheet. Yet, it is increasingly difficult to predict the power-performance accurately for the new architectures. We developed a fast and accurate power-performance methodology to predict block power-performance for 3nm and beyond nodes. This methodology was verified in imec's 2nm technology options such as Forksheet and semi-damascene BEOL processes. The results show excellent correlations with the performance-power gain of an ARM 64bit core.

Semi-damascene has been recently proposed as a candidate to replace dual-damascene for local routing layers in sub-3nm technology nodes. In this work, a block level design-technology co-optimization (DTCO) of semi-damascene is presented, evaluating the impact of different process options and design assumptions on performance, power, area and cost.Results show that semi-damascene not only outperforms dual- damascene in frequency and area, but it also provides a scalable path for further enhancements such as high density airgap and high aspect ratio wires, which promise even greater benefits.

Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.

The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF 63.2% (at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked.

We present local & global SRAM macro optimizations for 3nm FinFET and 2nm Nanosheet using Face-to-Face (F2F) and Wafer-to-Wafer (W2W) hybrid bonding at sub 1um pitch. Bonding pad parasitics are measured experimentally to calibrate RC models of the pad used to evaluate 3D-optimized memory macro delays. 3Doptimized macros are designed to reduce the macro external delay by ~50%. With customized SRAM BEOL, performance improvement of up to 70% for larger memories is observed compared with 2D macro. We also show that bit-cell tech-level optimizations have minor impact on the performance of large caches at advanced nodes due to high metal resistance in the macro global routing. Finally, at system-level we partition a L2 data memory (with 3D-optimized macro) from logic showing that the 3D implementation achieves a total of 33% performance gain with respect to a 2D implementation.

The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2× higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ω.cm 2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies.

To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the logic standard cell height (CH). However, limited scaling benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS to NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed achieving extremely scaled PN space using limited additional processing complexity. The FSH achieves 10% frequency increase at iso-power and 24% power reduction at iso-frequency compared to GAA nanosheet with a combined area scaling of 20%. SRAM bit cell area scaling of 30% and read delay performance increase is shown.

Scaling beyond 5nm will bring us into the post FinFET era where new device architectures optimized for CMOS logic scaling will be required. In this paper, the evolution to vertically stacked Nanosheets, Forksheet, and finally CFET are reviewed in conjunction with buried power rails and wrap around contact. Performance and area impact of these architectures are evaluated both at standard cell as well as block level to provide realistic PPA estimate for true technology scaling.

Advanced technology nodes employ a large number of innovations. In addition, they require `scaling boosters' in the design of standard-cell libraries to be able to offer the scaling benefits in area, performance, and power that we have grown accustomed to. Consequently, sub-10nm standard cells are significantly more complex than their predecessors. Cell-aware test (CAT) explicitly targets cell-internal resistive open and short defects identified through extensive characterization of the library cells. This paper is (to the best of our knowledge) the first to report on the application of CAT library characterization on a sub-10nm technology node. We used Cadence's CAT tool flow on an experimental 114-cell-library in IMEC's 3nm CMOS technology iN5. Despite the increased cell complexity, we show that the CAT flow still works, and that compared with functionally-comparable library cells in a 45nm technology, the number of potential non-equivalent defect locations, cell-level test patterns, and defect coverage did not change drastically.

The technology of buried power rails and back-side power delivery has been proposed for future scaling enablement, beyond the 5nm technology node. This paper studies the CPU design implications of power delivery in the context of these technologies. Employing standard VLSI design flows and sign-off techniques, we benchmark the power delivery designs and technology options using the Arm Cortex-A53 CPU at an imec 3nm technology node. DC and AC analyses of the resulting power delivery networks are presented for the various designs with buried power rails (with front-side and back-side power delivery) and compared to conventional designs without buried power rails. It is shown that buried rails with front-side power delivery can improve the worst-case IR drop from 70mV to 42mV (~1.7X reduction) while buried rails with back-side power delivery substantially reduce IR drop to 10mV (a 7X reduction).

Scaling beyond 5nm will bring us into the post FinFET era where new device architectures optimized for CMOS logic scaling will be required. In this paper, the evolution to vertically stacked Nanosheets, Forksheet, and finally CFET are reviewed in conjunction with buried power rails and wrap around contact. Performance and area impact of these architectures are evaluated both at standard cell as well as block level to provide realistic PPA estimate for true technology scaling.

We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low-k interconnects. The range of interconnect dimensions we cover spans from the 22 nm to the 3 nm logic technology node. We show that Ru and Co fills can significantly reduce resistance at narrow pitches. At 12 nm half-pitch, line and via resistance can be lowered by up to 36% and 75%, respectively, by replacing Cu with barrierless Ru fill; by using hybrid Cu metallization with Co via-prefill, at 12 nm half-pitch via resistance can be lowered by up to 42% in 87 degrees tapered vias and up to 52% in chamfered vias. As far as capacitance is concerned, Ru fill can enable interconnect schemes without dielectric liner. In this case, the line capacitance can be substantially reduced by using linerless replacement low-k or air-gap schemes, whose benefits become more significant at narrow pitches, when one accounts for low-k sidewall damage in conventional low-k schemes and takes these as a reference.

The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions of minimum island, via extension and tip-to-tip (T2T). Five-track place and route (PNR) and SRAM constructions were realized with the self-aligned block (SAB) technique. Stacked vias showed resistance modulation with the size of the minimum island due to the change in via chamfer. High aspect ratio supervias (SV), to bypass M2 and directly link M1 to M3, were tested with different metallization schemes. Line-to-line and T2T reliability tests passed the 10- year lifetime predictions. Finally, electromigration (EM) tests on SV showed no failures after 140 hours of accelerated stress conditions.

In imec predictive N5 technology platform (poly pitch 42nm, metal pitch 32nm), enabling cell height reduction from 6 to 5 tracks constitutes an interesting opportunity to reduce area of digital IP-blocks without increasing wafer cost. From a physical point of view, the two main challenges of reducing the number of tracks are posed by the increased difficulty of completing inter-cell connections in standard cell design, and by increased pin density that makes more challenging for the router to maintain high placement densities. Both these issues can potentially result into cell and chip area enlargement, thus mitigating or canceling the benefits of moving to 5-Tracks. In this study this side effect was avoided through a careful Design-Technology Co-Optimization approach (DTCO) [1], where a set of design arcs was used in conjunction with an EUV compatible ruleset that allowed efficient 5-Tracks standard cell design, resulting in final area gains up to 17% that were validated through a commercial state-of-the-art Place and Route (P&R) flow.

The increased complexity of CMOS transistor processing has led to limited scaling of high density SRAM cell at advanced technology nodes. STT-MRAM appears to be a promising candidate for replacing last level caches (LLC). This paper addresses design technology co-optimization (DTCO) of STT-MRAM technology and analyzes its viability as a LLC (compared to SRAM) for the high performance computing (HPC) domain (while maintaining a constraint of occupying merely 43.3% of SRAM macro area at identical capacities). This is the first study that breaks down a power, performance and area (PPA) comparison between SRAM and STT-MRAM based LLCs at the 5nm node. The STT-MRAM design and analysis is based on a silicon verified compact model and can be realized using 193i single patterning at the 5nm node. Our STT-MRAM design manages to achieve a nominal access latency <;2.5ns and <;7.1ns for read and write operations respectively. We also observe a clear and significant trend of increasing energy gains with respect to SRAM for increasing LLC sizes with the crossover points for STT-MRAM read and write operations at 0.4MB and 5MB respectively.

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide <50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm2 of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length.

With scaling of interconnect pitches in advanced process nodes, the ratio of line-edge roughness (LER) to line width increases. At the same time, the application of EUV lithography changes the characteristic LER parameters as compared to traditional lithography. In this paper, we provide an analysis of the impact of LER from wire resistance to system-level performance. Our silicon-calibrated resistance model is extended to include the effect of both LER standard deviation and correlation length, which allows accounting for the impact of wire length on resistance variability. The new resistance model is validated against Raphael simulations after process emulation by Sentaurus Process Explorer, with which realistic roughness can be reproduced by controlling the LER input parameters. A commercial CPU design is used as benchmark to assess system-level impact. After full physical implementation of the design, the impact of LER is modelled in a customized static timing analysis flow. Since LER is a stochastic effect, traditional corner-based modelling is not effective. Instead we propagate the wire resistance probabilities through the timing analysis to obtain a critical-path timing distribution and derive estimates for the impact on yield. Results show that while there is a significant impact of LER on the resistance distribution for short wires, the effect largely averages out on system level with the timing variation within 2 % of the clock period. The impact increases when scaling to narrower wires. In this case, we show that LER impact can be mitigated by using alternative mentalization schemes such as barrierless ruthenium interconnects.

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the router in terms of congestion and pin accessibility. To evaluate and downselect the best solutions, a holistic design-technology co-optimization approach leveraging state-of-the-art P&R tools is thus necessary. We adopt such an approach using the imec N7 technology platform, with contacted poly pitch of 42 nm and tightest metal pitch of 32 nm, by comparing post P&R area of an IP block for different standard cell configurations, technology options, and cell height. Keeping the technology node and the set of ground rules unchanged, we demonstrate that a careful combination of these solutions can enable area gains of up to 50%, comparable with the area benefits of migrating to another node. We further demonstrate that these area benefits can be achieved at isoperformance with >20% reduced power. As at the end of the CMOS roadmap, conventional scaling enacted through pitch reduction is made more and more challenging by constraints imposed by lithography limits, material resistivity, manufacturability, and ultimately wafer cost, the approach shown herein offers a valid, attractive, and low-cost alternative. (C) 2018 Society of Photo-Optical Instrumentation Engineers (SPIE)